Razr v3 critical error 12 01 8.29

razr v3 critical error 12 01 8.29

Designs. APPENDIX C-Critical Vlaues of the F-distribution 1. 2. 3 c) Linear graph: L8(21) Orthogonal Array a) Coded design matrix: 1 % 1. 1 Overview. This manual is a user guide to the gnu assembler as. Don't suppress warning messages or treat them as errors. //10/Logitech-MX-Keys-MX-Masterjpg Logitech MX Keys + MX Master 3 sprers.eu TZ.

Opinion: Razr v3 critical error 12 01 8.29

Razr v3 critical error 12 01 8.29
Razr v3 critical error 12 01 8.29
Razr v3 critical error 12 01 8.29
Run application-defined or object-defined error
Hp system error 86 01
@ GsmOrient,

Please run Prepare cycle exactly as written in manual.
Log file should be like this one:

Quote:

Switching to flash mode OK
Reading phone boot version A
Sending boot OK
Erasing flash memory OK
Sending firmware OK
Searching for phone found S Blank Neptune LTE2
Switching to flash mode OK
Reading phone boot version
About Clip Communiacation error: In case of getting an error "Clip communication failed", while detecting the handset, razr v3 critical error 12 01 8.29, please check the output of Smart-Clip power source. For stable Smart-Clip functions minimum output is 9V & mA. Recommended razr v3 critical error 12 01 8.29 supply is 12V & mA.

Some phone models use a data cable for charging. So, as soon as it gets connected to Smart-Clip it starts charging and uses about mA, razr v3 critical error 12 01 8.29, plus Clip requires another mA.

V3 with boot can be done via TP.

Best Regards
Smart-clip team
sprers.eu
sprers.eu
sprers.eu
sprers.eu


Last edited by sprers.eutrain; at

EPA4 - Synchronous read channel - Google Patents

SYNCHRONOUS READ CHANNEL

BACKGROUND OF THE INVENTION

In the storage or transmission of digital information, the bits or symbols of the user data are actually transmitted or stored via a physical media or mechanism whose responses are essentially analog in nature. The analog write or transmit signal going into the storage/transmission media or channel is typically modulated by channel bits (typically run-length limited or RLL bits) that are an encoded version of the original user-data bits (non-return-to-zero or NRZ bits). The analog read or receive signal coming from the media is demodulated to detect or extract estimated channel bits, which are then decoded into estimated user-data bits. Ideally, the estimated user-data bits would be an identical copy of the original user-data bits. In practice, they can be corrupted by distortion, timing variations, noise and flaws in the media and in the c+ + builder socket error # 11001 and read/receive channels.

The process of demodulating the analog read signal into a stream of estimated user-data bits can be implemented digitally. Digital demodulation in magnetic mass storage systems requires that the analog read signal be sampled at a rate that is on the order of the channel-bit rate. Maximum-likelihood (ML) demodulation is a process of constructing a best estimate of the channel bits that were written based on digitized samples captured from the analog read signal.

FIGURE 1 shows an exemplary read signalwhich is a positive-going pulse generated by an inductive read head, for example, from a single media transition such as transition from North-South to South-North magnetization of track on a rotating disk. Typically, the write signal modulates a transition in

SUBSTITUTESHEET the state of the media to write a channel bit of 1 and modulates the absence of a media transition to write a 0 channel atm err rak error trailer. Thus, transition corresponds to a single channel bit of value 1 in a stream of 0's.

It is common to use run-length-limited (RLL) encoding of the original user data bits, which are arbitrary or unconstrained, into an RLL-encoded stream of channel bits. It may be desirable that there be no less than d zeroes between ones; that is, that the media transitions be spaced by at least d+1 channel bit times. This constraint can help keep to a manageable level the interference effects among the pulses in the analog read signal. On the other hand, because media transitions provide timing information that must be extracted from the read signal to ensure synchronization of the demodulator with the pulses in the read signal, it may be desirable that there be no more than k zeroes between ones; that stop error c218, that there be a media transition at least every k'th channel bit time. An RLL(d,k) code is a code that can encode an arbitrary stream of original user- data bits into a stream of channel bits such that the encoded channel bit stream satisfies these two constraints. An RLL code has a theoretical capacity which limits the number of user bits which can be represented in a given number of RLL bits. The capacity is a function of the d and k constraints with d=0 and k=infinite being the limiting (unconstrained) case with a capacity of exactly one. The capacity of an RLL (1,7) code for example is just slightly greater than 2/3 and is exactly 2/3 for any practical implementation, meaning that every pair of user bits will map to exactly three RLL bits.

FIGURE 1, sample set shows the values of four samples in the case of side sampling of read signal ; i.e.,and Sample set is equivalent to the set 1, 3, 3, 1; that is, only the

SUBSTITUTESHEET ratios among samples are significant. A signal model gives rise to an expected sample sequence for a single or isolated transition in media state. Typically, only a few samples of an isolated media transition are non¬ zero; in this case, four are non-zero. In a side- sampled signal model such as 1, 3, 3, 1, timing circuitry in the demodulator attempts to maintain a lock on the incoming signal such that two adjacent samples on opposite sides of the peak of an isolated pulse have equal amplitudes and samples are taken at roughly equal time intervals, each a single channel bit time. Synchronization of the samples with the spacing of the bits written on the media is maintained by a timing recovery loop which is in essence a phase-locked loop. Other sample timing arrangements may be useful. In center sampling, the timing circuitry tries to lock the sample times to razr v3 critical error 12 01 8.29 read signal pulses such that one sample occurs at the peak of razr v3 critical error 12 01 8.29 pulse. Sample set shows the values of four samples in the case of center sampling of a similar read signal ; i.e.,razr v3 critical error 12 01 8.29, and (or, and depending on the arbitrary normalization used). An expected sample sequence of 1, 2, 1, 0 corresponds to the signal model known in the prior art as Extended Partial-Response Class IV (EPR4). Such sample sequences are samples of a continuous-time analog read-signal waveform such as may be produced in the readback circuitry of a magnetic storage device. For a system that is bandwidth limited to 1/ (2T)where T is the sample spacing in time, the sampling theorem declares that the continuous time waveform must be superposition of sine functions (sinc(x) is defined as sin(x)/x for xo0, and as 1 for x=0), with one sine function centered at each sample point and of amplitude equal to that sample value and with zero crossings at all other sample points. As an example, in saturation magnetic recording, the current

SUBSTITUTESHEET in an inductive write head takes, on values of +1 and The basic excitation applied to the recording channel is a step in current from +1 to -1, vice versa, in the analog write signal. This step in write current produces a transition in the magnetization state of the media as it moves past the head. When an inductive read head is passed over this magnetic media transition, a voltage pulse is induced by the bandwidth limited differentiating interaction of the head with the magnetization of the media. By suitable filtering or equalization, the sequence of samples on an isolated transition response pulse can be made to {, 0, 0, 1, 2, 1, 0, 0, }, in which case the recording or transmission channel matches the EPR4 signal model. Another sam l-; sequence well known in the prior art is the Partial Response Class IV signal model (PR4), which corresponds to an expected sample sequence of 0, 1, 1, 0. Further, as one is designing or taking measurements on a write/media/read channel, it may be desirable to take into account the exact response, noise and distortion characteristics of the channel in selecting the signal model to be implemented in the demodulator. Thus, there is a need for a demodulator that is programmable as to the signal model, or expected sequence of sample values for an isolated media transition. In situations such as mass information storage in magnetic media, significant storage-system speed and capacity gains can be realized if the information bits can be closer together in position/time on the media. further, as media transitions are more closely positioned, the writing and reading processes become more sensitive to the distortion, razr v3 critical error 12 01 8.29, timing variations and noise that are inevitably introduced in the processes of writing, storing, and reading. Also, as the transitions become closer, the ability of the media to fully transition from, say, North-South

SUBSTITUTESHEET magnetization to South-North magnetization may be taxed. Also, razr v3 critical error 12 01 8.29, as the media transitions become closer, interference effects increase among adjacent or nearby transitions. FIGURE 2 shows how positive-going pulse from first media transition combines with negative-going pulse from second transition to produce analog read signalwhich can be viewed as the interference of razr v3 critical error 12 01 8.29 two pulses. Adjacent media transitions always give rise to read pulses of opposite polarities because they always are created by transitions of opposite types, for example North-South changes to South-North in transitionso adjacent transition must be South-North changing back to North-South. Read signal might give rise to a sequence of samples such as,To the extent that the read process is linear (and it may not be entirely linear)the voltage waveform induced in the read head will be the superposition of a sequence of pulses, where each pulse is the response to an isolated magnetic transition on the media. Clearly, engineering a high-performance read channel is a complex challenge given the combined effects of the limited sampling rate in a digital demodulator, possibly incomplete transitions in the media, interference among read-signal responses to media transitions, and distortion, timing variations, noise and flaws in the media and in the write and read channels. The prior art uses a method known as partial- response signaling to increase media transition rates. Partial-response signaling is described in the book "Digital Transmission of Information", by Richard E. Blahut,pp. and This method allows the analog response of the storage/transmission media and of the write/transmit and read/receive circuitry to a media transition to overlap with the response to adjacent transitions associated with

SUBSTITUTE SHEET subsequent information bits. If properly implemented, this method can achieve higher information bit rates/densities than the alternative or requiring the media transitions to be spaced such that the read signal responses do not overlap. Such a method requires a sequence detector which can make its decisions not on a bit-by-bit basis but by examining the context of the surrounding read signal.

In a magnetic disk drive, the surface of the magnetic media is logically divided into concentric rings called tracks. The distance around the track varies as a function of the radius at which the track lies. Since it is desirable to keep the rate of revolution of the disk constant to avoid mechanical delays in accelerating and decelerating the disk, it is necessary to either store an amount of data on each track which is proportional to the length of the track (this requires a different data transfer rate for 500 internal server error error was track) or to vary the physical transition spacing on the media so that pulses are widely separated at the outside diameter and crowded very close at the inner diameter of the recording surface (this is wasteful of the magnetic media which is only sparsely used at the error unable to update user visit data diameter). A practice known as zoned recording is a popular compromise between these two extremes. In zoned recording, a group of tracks (a zone) is established in which every track in the zone holds the same amount of data. Thus each zone requires samsung galaxy ace wifi error solution different data transfer rate, but the number of data transfer rates which need be supported is reduced (more coarsely quantized)razr v3 critical error 12 01 8.29. This still leaves a variation in the physical spacing of transitions between the inside and outside diameters of each zone resulting in a variation in pulse shape.

Partial-response signaling has just recently been incorporated into mass storage devices and then in a limited form. One prior-art magnetic disk drive using

SUBSTITUTESHEET partial-response signaling only supports PR4 (pulses with the samples of0, razr v3 critical error 12 01 8.29, 1, 0, ). PR4 signaling has only very limited inter-symbol interference evidenced by only two non-zero samples in the pulse. To increase the capacity of the media, the user of a PR4 read channel must increase the equalization of the pulses (slim the pulses) in order to limit the inter-symbol interference of adjacent pulses so that any pulse only affects two read signal samples. The increased equalization also enhances the noise accompanying the signal, making the detection task more difficult and errors more likely. U.S. Patent 4, by Patel covers a similar situation but with EPR4 signaling and an RLL(1,7) code. This improves the allowed amount of inter-symbol interference, increasing it to three non-zero samples of (, 0, 1/2, 1, 1/2, 0, ). Both dayz error creating direct3d these techniques will allow an increase in capacity but are limited in the variety of pulse shapes which can be detected and therefore limited by how much equalization (pulse slimming) may be performed before the effect of equalizing the noise (noise enhancement) becomes intolerable.

Thus, there is a need for a flexible read channel which can accommodate a wide variety of pulse shapes as will be seen in each zone. There is also a need to allow larger amounts of controlled inter-symbol interference between pulses (pulses with more than two or three non-zero pulses) in order to continue increasing the capacity of the recording media.

SUBSTITUTE SHEET SUMMARY OF THE INVENTION

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

SUBSTITUTESHEET BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a state transition on a medium such as a track of a disk drive and its associated pulse in an analog read signal. It also shows two digitized sample models of such read-signal pulses.

FIGURE 2 shows two adjacent medium transitions and their individual and combined read-signal pulses.

Figure 3 is an overall block diagram of the present invention.

Figure 4 is a block diagram illustrating the details of the gain control circuit 32 of Figure 3.

Figure 5 is a block diagram illustrating the details of the timing recovery circuit 34 of Figure 3.

Figure 6 is a block diagram illustrating the details of the spectrum smoothing filter 42 of Figure 3.

SUBSTITUTE SHEET DETAILED DESCRIPTION OF THE INVENTION

The CL-SH is a specific embodiment of the present invention designed to work with a companion analog integrated circuit and a disk controller to form a state of the art high density magnetic disk drive. In that regard, the uniqueness razr v3 critical error 12 01 8.29 the present invention, while used in a digital read-write channel, is primarily related to its read capability and versatility.

The companion integrated circuit with which the CL- SH is specifically intended to operate implements a VGA (Variable Gain Amplifier)a tunable analog filter, an analog to digital converter, a timing VFO (Variable Frequency Oscillator)write pre-compensation and servo demodulation functions. Accordingly, in a read operation, the CL-SH does not receive an analog signal but instead receives already digitized read information in the form of digitized analog read channel samples. Further, while the timing Variable Frequency Oscillator and the Variable Gain Amplifier are on the companion integrated circuit and are not part of the present invention, the timing VFO and the Variable Gain Amplifier are each digitally controlled through digital control signals generated in the CL-SH Accordingly, in the specific embodiment to be described, digital control feedback signals for both the VFO and the VGA are generated in the CL-SH even though the control loops for the timing recovery and the automatic gain control functions are actually closed within the companion analog integrated circuit. In that regard, it should be particularly noted that the automatic gain control signal may alternatively be generated on the analog companion integrated circuit, as the same may be readily generated in the analog domain rather than in the digital domain. Accordingly, particularly the

SUBSTITUTE SHEET generation of the digital gain control to be described as part of the CL-SH is an optional design choice readily relegated to the companion integrated circuit if desired.

Figure 3 provides a block diagram illustrating the general organization of the CL-SH As may be seen in Figure 3, razr v3 critical error 12 01 8.29, the digitized read data for the CL-SH is provided in an N-bit parallel form as digitized read data DRDO and DRD1. Each of these two signals in the preferred embodiment disclosed is a 6-bit digitized read data signal. These two N-bit signals represent digitized samples of a read signal directly from a read head of the storage device after analog amplification and analog filtering. Those skilled in the art will recognize that the purpose of the analog amplifier and the analog filter is to scale the signals to the input range of the digital to analog converter and to attenuate frequencies above the Nyquist frequency (1/2 the sample frequency) to avoid signal distortion due to aliasing. In general, the analog filter will perform pulse shaping as well. The digitized read data signal DRDO is a digitized read signal sample effectively taken near the center of a channel bit time (defined by the VFO frequency)subject however to a small amount of timing error or intentional timing set point offset in the VFO. The digitized read data signal DRD1 is the corresponding digitized read sample effectively taken near the center time of the previous logical channel bit, subject of course to similar timing errors and timing set point offsets. These two digitized read data signals are processed in the CL-SH in a parallel or simultaneous manner so that ultimately in the CL-SH, two successive bits of digital read data will be derived from one set of DRDO and DRD1 signals which together with successive bit pairs are decoded by a run-length limited (RLL) decoder and derandomized if applicable

SUBSTITUTESHEET (e.g. if initially randomized) to provide the NRZ data output stream of the device. The processing of two digitized read data samples simultaneously doubles the throughput of the CL-SH for a given clock rate without doubling the circuitry required, particularly in the sequence detector, though the present invention is not specifically limited to processing of two digitized read data sample at a time. One could process one digitized read data sample at a time, or alternatively process more than two digitized read data samples at a1 time, if desired. In that regard, the number of N-bit digitized read data sample connections to the chip normally will equal the number of samples processed at a time, though such signals could be multiplexed so that the number of N-bit digitized read data samples connections to the chip is less than the number of samples processed together.

In one mode of operation, multiplexer 28 couples the DRDO and DRD1 signals directly to a transition detector 22 which processes the successive samples to detect the presence of transitions in each of the two digitized read data signals. The output of the transition detector is a low or high level during the respective bit times (delayed as described in the co¬ pending application) depending upon whether a transition (providing a high level output) or no transition (providing a low level output) was detected. The output of the transition detector 22, razr v3 critical error 12 01 8.29, the peak detected signal PKDET, in this mode would be coupled to multiplexer 24 and through a sync mark detector 26 to provide a sync byte detected output SBD if a sync byte was in fact detected, and to couple the two bits to the RLL decoder 28 which decodes the bit stream to provide the NRZ data out digital data. In the preferred embodiment run length constraint violations are detected and optionally multiplexed onto the NRZ data out lines. These may be

Razr v3 critical error 12 01 8.29 - consider, that

@ GsmOrient,

Please run Prepare cycle exactly as written in manual.
Log file should be like this one:

Quote:

Switching to flash mode OK
Reading phone boot version A
Sending boot OK
Erasing flash memory OK
Sending firmware OK
Searching for phone found S Blank Neptune LTE2
Switching to flash mode OK
Reading phone boot version
About Clip Communiacation error: In case of getting an error "Clip communication failed", while detecting the handset, please check the output of Smart-Clip power source. For stable Smart-Clip functions minimum output is 9V & mA. Recommended power supply is 12V & mA.

Some phone models use a data cable for charging. So, as soon as it gets connected to Smart-Clip it starts charging and uses about mA, plus Clip requires another mA.

V3 with boot can be done via TP.

Best Regards
Smart-clip team
sprers.eu
sprers.eu
sprers.eu
sprers.eu


Last edited by sprers.eutrain; at

EPA4 - Synchronous read channel - Google Patents

SYNCHRONOUS READ CHANNEL

BACKGROUND OF THE INVENTION

In the storage or transmission of digital information, the bits or symbols of the user data are actually transmitted or stored via a physical media or mechanism whose responses are essentially analog in nature. The analog write or transmit signal going into the storage/transmission media or channel is typically modulated by channel bits (typically run-length limited or RLL bits) that are an encoded version of the original user-data bits (non-return-to-zero or NRZ bits) . The analog read or receive signal coming from the media is demodulated to detect or extract estimated channel bits, which are then decoded into estimated user-data bits. Ideally, the estimated user-data bits would be an identical copy of the original user-data bits. In practice, they can be corrupted by distortion, timing variations, noise and flaws in the media and in the write/transmit and read/receive channels.

The process of demodulating the analog read signal into a stream of estimated user-data bits can be implemented digitally. Digital demodulation in magnetic mass storage systems requires that the analog read signal be sampled at a rate that is on the order of the channel-bit rate. Maximum-likelihood (ML) demodulation is a process of constructing a best estimate of the channel bits that were written based on digitized samples captured from the analog read signal.

FIGURE 1 shows an exemplary read signal , which is a positive-going pulse generated by an inductive read head, for example, from a single media transition such as transition from North-South to South-North magnetization of track on a rotating disk. Typically, the write signal modulates a transition in

SUBSTITUTESHEET the state of the media to write a channel bit of 1 and modulates the absence of a media transition to write a 0 channel bit. Thus, transition corresponds to a single channel bit of value 1 in a stream of 0's.

It is common to use run-length-limited (RLL) encoding of the original user data bits, which are arbitrary or unconstrained, into an RLL-encoded stream of channel bits. It may be desirable that there be no less than d zeroes between ones; that is, that the media transitions be spaced by at least d+1 channel bit times. This constraint can help keep to a manageable level the interference effects among the pulses in the analog read signal. On the other hand, because media transitions provide timing information that must be extracted from the read signal to ensure synchronization of the demodulator with the pulses in the read signal, it may be desirable that there be no more than k zeroes between ones; that is, that there be a media transition at least every k'th channel bit time. An RLL(d,k) code is a code that can encode an arbitrary stream of original user- data bits into a stream of channel bits such that the encoded channel bit stream satisfies these two constraints. An RLL code has a theoretical capacity which limits the number of user bits which can be represented in a given number of RLL bits. The capacity is a function of the d and k constraints with d=0 and k=infinite being the limiting (unconstrained) case with a capacity of exactly one. The capacity of an RLL (1,7) code for example is just slightly greater than 2/3 and is exactly 2/3 for any practical implementation, meaning that every pair of user bits will map to exactly three RLL bits.

FIGURE 1, sample set shows the values of four samples in the case of side sampling of read signal ; i.e. , , , and Sample set is equivalent to the set 1, 3, 3, 1; that is, only the

SUBSTITUTESHEET ratios among samples are significant. A signal model gives rise to an expected sample sequence for a single or isolated transition in media state. Typically, only a few samples of an isolated media transition are non¬ zero; in this case, four are non-zero. In a side- sampled signal model such as 1, 3, 3, 1, timing circuitry in the demodulator attempts to maintain a lock on the incoming signal such that two adjacent samples on opposite sides of the peak of an isolated pulse have equal amplitudes and samples are taken at roughly equal time intervals, each a single channel bit time. Synchronization of the samples with the spacing of the bits written on the media is maintained by a timing recovery loop which is in essence a phase-locked loop. Other sample timing arrangements may be useful. In center sampling, the timing circuitry tries to lock the sample times to the read signal pulses such that one sample occurs at the peak of each pulse. Sample set shows the values of four samples in the case of center sampling of a similar read signal ; i.e., , , , and (or , , and depending on the arbitrary normalization used) . An expected sample sequence of 1, 2, 1, 0 corresponds to the signal model known in the prior art as Extended Partial-Response Class IV (EPR4) . Such sample sequences are samples of a continuous-time analog read-signal waveform such as may be produced in the readback circuitry of a magnetic storage device. For a system that is bandwidth limited to 1/ (2T) , where T is the sample spacing in time, the sampling theorem declares that the continuous time waveform must be superposition of sine functions (sinc(x) is defined as sin(x)/x for xo0, and as 1 for x=0), with one sine function centered at each sample point and of amplitude equal to that sample value and with zero crossings at all other sample points. As an example, in saturation magnetic recording, the current

SUBSTITUTESHEET in an inductive write head takes, on values of +1 and The basic excitation applied to the recording channel is a step in current from +1 to -1, vice versa, in the analog write signal. This step in write current produces a transition in the magnetization state of the media as it moves past the head. When an inductive read head is passed over this magnetic media transition, a voltage pulse is induced by the bandwidth limited differentiating interaction of the head with the magnetization of the media. By suitable filtering or equalization, the sequence of samples on an isolated transition response pulse can be made to {, 0, 0, 1, 2, 1, 0, 0, }, in which case the recording or transmission channel matches the EPR4 signal model. Another sam l-; sequence well known in the prior art is the Partial Response Class IV signal model (PR4), which corresponds to an expected sample sequence of 0, 1, 1, 0. Further, as one is designing or taking measurements on a write/media/read channel, it may be desirable to take into account the exact response, noise and distortion characteristics of the channel in selecting the signal model to be implemented in the demodulator. Thus, there is a need for a demodulator that is programmable as to the signal model, or expected sequence of sample values for an isolated media transition. In situations such as mass information storage in magnetic media, significant storage-system speed and capacity gains can be realized if the information bits can be closer together in position/time on the media. further, as media transitions are more closely positioned, the writing and reading processes become more sensitive to the distortion, timing variations and noise that are inevitably introduced in the processes of writing, storing, and reading. Also, as the transitions become closer, the ability of the media to fully transition from, say, North-South

SUBSTITUTESHEET magnetization to South-North magnetization may be taxed. Also, as the media transitions become closer, interference effects increase among adjacent or nearby transitions. FIGURE 2 shows how positive-going pulse from first media transition combines with negative-going pulse from second transition to produce analog read signal , which can be viewed as the interference of the two pulses. Adjacent media transitions always give rise to read pulses of opposite polarities because they always are created by transitions of opposite types, for example North-South changes to South-North in transition , so adjacent transition must be South-North changing back to North-South. Read signal might give rise to a sequence of samples such as , , , , , To the extent that the read process is linear (and it may not be entirely linear) , the voltage waveform induced in the read head will be the superposition of a sequence of pulses, where each pulse is the response to an isolated magnetic transition on the media. Clearly, engineering a high-performance read channel is a complex challenge given the combined effects of the limited sampling rate in a digital demodulator, possibly incomplete transitions in the media, interference among read-signal responses to media transitions, and distortion, timing variations, noise and flaws in the media and in the write and read channels. The prior art uses a method known as partial- response signaling to increase media transition rates. Partial-response signaling is described in the book "Digital Transmission of Information", by Richard E. Blahut, , pp. and This method allows the analog response of the storage/transmission media and of the write/transmit and read/receive circuitry to a media transition to overlap with the response to adjacent transitions associated with

SUBSTITUTE SHEET subsequent information bits. If properly implemented, this method can achieve higher information bit rates/densities than the alternative or requiring the media transitions to be spaced such that the read signal responses do not overlap. Such a method requires a sequence detector which can make its decisions not on a bit-by-bit basis but by examining the context of the surrounding read signal.

In a magnetic disk drive, the surface of the magnetic media is logically divided into concentric rings called tracks. The distance around the track varies as a function of the radius at which the track lies. Since it is desirable to keep the rate of revolution of the disk constant to avoid mechanical delays in accelerating and decelerating the disk, it is necessary to either store an amount of data on each track which is proportional to the length of the track (this requires a different data transfer rate for each track) or to vary the physical transition spacing on the media so that pulses are widely separated at the outside diameter and crowded very close at the inner diameter of the recording surface (this is wasteful of the magnetic media which is only sparsely used at the outer diameter) . A practice known as zoned recording is a popular compromise between these two extremes. In zoned recording, a group of tracks (a zone) is established in which every track in the zone holds the same amount of data. Thus each zone requires a different data transfer rate, but the number of data transfer rates which need be supported is reduced (more coarsely quantized) . This still leaves a variation in the physical spacing of transitions between the inside and outside diameters of each zone resulting in a variation in pulse shape.

Partial-response signaling has just recently been incorporated into mass storage devices and then in a limited form. One prior-art magnetic disk drive using

SUBSTITUTESHEET partial-response signaling only supports PR4 (pulses with the samples of , 0, 1, 1, 0, ). PR4 signaling has only very limited inter-symbol interference evidenced by only two non-zero samples in the pulse. To increase the capacity of the media, the user of a PR4 read channel must increase the equalization of the pulses (slim the pulses) in order to limit the inter-symbol interference of adjacent pulses so that any pulse only affects two read signal samples. The increased equalization also enhances the noise accompanying the signal, making the detection task more difficult and errors more likely. U.S. Patent 4,, by Patel covers a similar situation but with EPR4 signaling and an RLL(1,7) code. This improves the allowed amount of inter-symbol interference, increasing it to three non-zero samples of (, 0, 1/2, 1, 1/2, 0, ) . Both of these techniques will allow an increase in capacity but are limited in the variety of pulse shapes which can be detected and therefore limited by how much equalization (pulse slimming) may be performed before the effect of equalizing the noise (noise enhancement) becomes intolerable.

Thus, there is a need for a flexible read channel which can accommodate a wide variety of pulse shapes as will be seen in each zone. There is also a need to allow larger amounts of controlled inter-symbol interference between pulses (pulses with more than two or three non-zero pulses) in order to continue increasing the capacity of the recording media.

SUBSTITUTE SHEET SUMMARY OF THE INVENTION

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

SUBSTITUTESHEET BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a state transition on a medium such as a track of a disk drive and its associated pulse in an analog read signal. It also shows two digitized sample models of such read-signal pulses.

FIGURE 2 shows two adjacent medium transitions and their individual and combined read-signal pulses.

Figure 3 is an overall block diagram of the present invention.

Figure 4 is a block diagram illustrating the details of the gain control circuit 32 of Figure 3.

Figure 5 is a block diagram illustrating the details of the timing recovery circuit 34 of Figure 3.

Figure 6 is a block diagram illustrating the details of the spectrum smoothing filter 42 of Figure 3.

SUBSTITUTE SHEET DETAILED DESCRIPTION OF THE INVENTION

The CL-SH is a specific embodiment of the present invention designed to work with a companion analog integrated circuit and a disk controller to form a state of the art high density magnetic disk drive. In that regard, the uniqueness of the present invention, while used in a digital read-write channel, is primarily related to its read capability and versatility.

The companion integrated circuit with which the CL- SH is specifically intended to operate implements a VGA (Variable Gain Amplifier) , a tunable analog filter, an analog to digital converter, a timing VFO (Variable Frequency Oscillator) , write pre-compensation and servo demodulation functions. Accordingly, in a read operation, the CL-SH does not receive an analog signal but instead receives already digitized read information in the form of digitized analog read channel samples. Further, while the timing Variable Frequency Oscillator and the Variable Gain Amplifier are on the companion integrated circuit and are not part of the present invention, the timing VFO and the Variable Gain Amplifier are each digitally controlled through digital control signals generated in the CL-SH Accordingly, in the specific embodiment to be described, digital control feedback signals for both the VFO and the VGA are generated in the CL-SH even though the control loops for the timing recovery and the automatic gain control functions are actually closed within the companion analog integrated circuit. In that regard, it should be particularly noted that the automatic gain control signal may alternatively be generated on the analog companion integrated circuit, as the same may be readily generated in the analog domain rather than in the digital domain. Accordingly, particularly the

SUBSTITUTE SHEET generation of the digital gain control to be described as part of the CL-SH is an optional design choice readily relegated to the companion integrated circuit if desired.

Figure 3 provides a block diagram illustrating the general organization of the CL-SH As may be seen in Figure 3, the digitized read data for the CL-SH is provided in an N-bit parallel form as digitized read data DRDO and DRD1. Each of these two signals in the preferred embodiment disclosed is a 6-bit digitized read data signal. These two N-bit signals represent digitized samples of a read signal directly from a read head of the storage device after analog amplification and analog filtering. Those skilled in the art will recognize that the purpose of the analog amplifier and the analog filter is to scale the signals to the input range of the digital to analog converter and to attenuate frequencies above the Nyquist frequency (1/2 the sample frequency) to avoid signal distortion due to aliasing. In general, the analog filter will perform pulse shaping as well. The digitized read data signal DRDO is a digitized read signal sample effectively taken near the center of a channel bit time (defined by the VFO frequency) , subject however to a small amount of timing error or intentional timing set point offset in the VFO. The digitized read data signal DRD1 is the corresponding digitized read sample effectively taken near the center time of the previous logical channel bit, subject of course to similar timing errors and timing set point offsets. These two digitized read data signals are processed in the CL-SH in a parallel or simultaneous manner so that ultimately in the CL-SH, two successive bits of digital read data will be derived from one set of DRDO and DRD1 signals which together with successive bit pairs are decoded by a run-length limited (RLL) decoder and derandomized if applicable

SUBSTITUTESHEET (e.g. if initially randomized) to provide the NRZ data output stream of the device. The processing of two digitized read data samples simultaneously doubles the throughput of the CL-SH for a given clock rate without doubling the circuitry required, particularly in the sequence detector, though the present invention is not specifically limited to processing of two digitized read data sample at a time. One could process one digitized read data sample at a time, or alternatively process more than two digitized read data samples at a1 time, if desired. In that regard, the number of N-bit digitized read data sample connections to the chip normally will equal the number of samples processed at a time, though such signals could be multiplexed so that the number of N-bit digitized read data samples connections to the chip is less than the number of samples processed together.

In one mode of operation, multiplexer 28 couples the DRDO and DRD1 signals directly to a transition detector 22 which processes the successive samples to detect the presence of transitions in each of the two digitized read data signals. The output of the transition detector is a low or high level during the respective bit times (delayed as described in the co¬ pending application) depending upon whether a transition (providing a high level output) or no transition (providing a low level output) was detected. The output of the transition detector 22, the peak detected signal PKDET, in this mode would be coupled to multiplexer 24 and through a sync mark detector 26 to provide a sync byte detected output SBD if a sync byte was in fact detected, and to couple the two bits to the RLL decoder 28 which decodes the bit stream to provide the NRZ data out digital data. In the preferred embodiment run length constraint violations are detected and optionally multiplexed onto the NRZ data out lines. These may be

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