Flash ctrl error

flash ctrl error

Download Citation | Method of eliminating synchronism control error in flash butt welding of bill | Based on the characteristics and the demands of. The flash controller provides flash configuration and control functions and manages the interface between the flash memory array and the device crossbar switch. Based on the error messages you are getting, it looks like your flash is in depletion. It also looks like your depletion recovery algorithm also.

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Flash ctrl error
Typical computer errors
SCAN FAILED ERROR CODE 0

US8213229B2 - Error control in a flash memory device - Google Patents

1. Field of the Invention

The invention is related to the field of flash memory devices. More particularly, flash ctrl error, the invention relates to controlling data errors in the devices through various forms of decoding, error correction, and “wear concentration”.

2. Statement of the Problem

Flash memory is non volatile computer memory that can be electrically erased and reprogrammed and does not require power to maintain stored information. Additionally, flash ctrl error, flash memory offers relatively fast read access times and generally better kinetic shock resistance than hard disks, flash ctrl error. Another feature of flash memory is its durability, being able to withstand intense pressure, extreme temperatures, and even immersion in water. Such features are clearly advantageous to portable devices, such as cell phones, flash ctrl error, portable digital assistants (PDAs), and media players, such as the Apple, Inc. iPod.

Flash memory devices typically contain user data areas and overhead data areas. Such overhead information typically includes erase block management data and/or sector status information. Erase block management of a flash memory device generally provides logical sector to physical sector mapping.

Flash memory devices experience a greater incidence of errors than other forms of media due to increased memory cell densities, manufacturing inconsistencies, lower operating voltages, and, flash ctrl error, more particularly, excessive use of the devices. For instance, flash memory devices experience write fatigue over time which leads to less data integrity.

In some instances, flash memory devices are abstracted by various software drivers, management routines, and hardware support circuitry to hide defective regions from host systems to counter the errors. This abstraction of the memory device or computer usable storage is generally accomplished through the marking of bad memory blocks and their subsequent replacement with spare memory blocks. Additionally, flash ctrl error, error correction codes (ECCs) may be used to detect and correct data errors in retrieved data. ECCs may include block codes that are associated with a block of stored data or a data sector and stream codes that are typically utilized with streams of transmitted data. Error correction of data is generally done by a microprocessor or specialized hardware configured as an external microprocessor, flash ctrl error, a memory controller or within the memory device itself, flash ctrl error. Error correction is relatively complex and fairly processor intensive.

ECCs, and block codes in particular, are commonly based on specialized polynomial equations. Examples of such ECCs include Hamming codes, Reed-Solomon codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, and cyclic redundancy check (CRC) codes. When the data is read out of a memory, the data integrity is checked by regenerating the coefficients embedded with the read data. The read data is passed through an ECC generator/checker to regenerate the ECC for comparison to the coefficients of the stored ECC. Flash ctrl error the generated and stored ECCs do not match, an error has been detected. Once an error in the read data is detected, the transfer of the data out of the memory device is halted and the ECC correction algorithm initiates to correct the data error. However, an overhead cost is associated with the ECC. These overhead costs come in the form of increased storage space required for storing the ECC codes to allow detection and correction flash ctrl error errors in the stored data. In other words, ECCs generally require the association of extra bits to data and thus take away from flash ctrl error space available for data storage in a memory device.

Generally, the number of bits of an ECC determines the number of errors that can be detected and/or corrected. For instance, 1-bit ECC algorithms enable a set of symbols to be represented such that if one bit of the representation is incorrect, or “flipped”, the symbols will be corrected, flash ctrl error. 2-bit ECC algorithms enable a set of symbols to be represented such that if two bits of the representation are flipped or otherwise incorrect, the two bits will be corrected. Often, the use of a 2-bit ECC algorithm is preferred to a 1-bit ECC algorithm due to the ability of a 2-bit ECC algorithm to detect and correct more bits. However, the implementation of a 2-bit ECC algorithm, while providing increased error correction capabilities of stored data, generally involves more calculations and overhead than the implementation of a 1-bit ECC algorithm. When more computational overhead is required, more power is consumed by the flash memory device. As a result, flash ctrl error, the overall performance of a memory system may be compromised.

To reduce the computational and power requirements associated with implementing a 2-bit ECC algorithm, some systems may flash ctrl error 1-bit ECC algorithms to encode and to decode data, even though such algorithms are less accurate. In many cases, when a block is fairly new and has not been subjected to a relatively high number of erase/write cycles, flash ctrl error, a 1-bit ECC algorithm may be sufficient to ensure the integrity of much of the data. However, as a block gets older and subjected to a relatively high number of the erase/write cycles, a 1-bit ECC algorithm may not be sufficient to ensure a desired level of data integrity.

A hybrid ECC implementation enables a 1-bit ECC encoding and decoding of data in blocks which have undergone a relatively low flash ctrl error of erase/write cycles. For blocks which have undergone a relatively high number of erase/write cycles, a 2-bit ECC encoding and decoding of data is used. By dynamically determining when data is to be encoded using a more accurate algorithm, storage capacity decreases over time as opposed to an initial decrease of storage capacity through the use of a long term ECC algorithm, flash ctrl error. Moreover, the power requirements of the flash memory device increase over time via the dynamic allocation of ECC rather than the immediate power consumption associated with a larger ECC.

To implement the hybrid ECC algorithm, the flash memory device uses a threshold count of a number of erase/write cycles as an indicator of when to use a less calculation-intensive/lower accuracy ECC algorithm or a more calculation-intensive/higher accuracy ECC algorithm to encode data. For instance, when a comparison of the number of erase/write cycles undergone by a block breaches a threshold number of 100,000 erase/write cycles, then a higher accuracy ECC algorithm is used. In any case, the dynamic allocation of ECC still requires that space be allocated from the flash memory device thus reducing the overall capacity of the device.

Another manner of extending the usable life of the flash memory device regards the implementation of “wear leveling”. Wear leveling attempts to arrange data so that erasures and re-writes are distributed evenly across the flash memory cells of the flash device. In this way, no single sector prematurely fails due to a high concentration of erase/write cycles, flash ctrl error. A problem, however, exists with wear leveling as it still results in a substantial decrease in storage capacity over the useful life of the device by quickly decreasing the storage capacity of individual cells.

Embodiments of the invention operate to control errors within a flash memory device. In this regard, various systems and methods described herein provide for “wear concentration” and decoding of data within the flash memory device. The wear concentration aspect of the invention partitions the flash memory device into a plurality of data sectors. Data is then stored in these sectors based on their write frequencies and/or their storage durations. Data with shorter storage durations is stored in predetermined partitions such that those flash memory cells flash ctrl error away faster. However, the average storage capacity of the flash memory cells is greater over time when compared to wear leveling. The decoding aspect of the invention selects candidate data sequences to represent data read from the flash memory cells of the device with errors.

In one embodiment of the invention, a method of using a flash memory device includes partitioning the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations, flash ctrl error. The method also apache 404 error page receiving first data to be written to the flash memory device. The method also includes estimating a storage duration for the first data and storing the first data in the first sector based on the estimated storage duration of the first data.

In another embodiment, a flash ctrl error memory system includes an array of flash memory cells and a partitioner adapted to partition the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second sector is flash ctrl error to store data having a second range of storage durations that is different than the first range of storage durations. The flash memory system also includes a data flash ctrl error communicatively coupled to the partitioner and adapted to receive first data for storage in the flash memory cells, estimate a storage duration for the first data, and store the first data in the first sector based on the estimated storage duration of the first data.

The invention may include other exemplary embodiments described below.

and the following description depict specific exemplary embodiments of the invention to teach those skilled in the art how to make and use the invention. For the purpose of teaching inventive principles, some conventional aspects of the invention have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the invention. As a result, the invention is not flash ctrl error to the specific embodiments described below, but only by the claims and their equivalents.

shows a block diagram of flash memory device 100 including an array of flash memory cells 103. Flash memory device 100 also includes host processor 104 that provides for general control of flash memory device 100. Flash memory cells 103 are individually addressable and arranged in the array in rows and columns, flash ctrl error. In this regard, host processor 104 also includes control logic 105 that interfaces with the array of flash memory cells 103 via row decoder 102 and column decoder 101. Individual flash memory cells 103 are controlled flash ctrl error word lines 114 that extend along the rows of the array and bit lines 113 that extend along columns of the array. During a read access, a row address is latched and decoded by row decoder 102, error only one processor found selects and activates a “row page” of memory cells 103 for transfer via interface 112. The column address of the read access is latched and decoded by column decoder 101. Column decoder 101 then selects the specified column data from flash memory cells 103 for transfer via interface 111. Similarly, during a write access, row decoder 102 selects a row page of flash memory cells 103 for writing whereas column decoder 101 selects a column address of flash memory cells 103 for writing.

In addition to general read and write operations to the array of flash memory cells 103, control logic 105 also performs certain functions that advantageously extend the “useful life” of flash memory cells 103. For instance, flash memory cells 103 may be subject to “wear” as the number of writes and erasures to the cells increase over time, flash ctrl error. This wear of flash memory cells 103 causes an increase in the number of flash ctrl error in data being read from flash memory cells 103 over time. These errors can be corrected through the use of error correction codes and managed by wear leveling techniques, as mentioned above. At some point, however, these methods for extending the life of flash memory cells 103 become impractical due to power considerations, flash ctrl error, storage constraints, etc. In this regard, control logic 105 may extend the useful life of flash memory cells 103 via novel “wear concentration” and decoding processes.

To perform wear concentration, control logic 105 may include data analyzer 110 for analyzing write data to be written to flash memory cells 103. Data analyzer 110 estimates storage durations of the data such that data with shorter storage durations may be concentrated into certain designated areas of the array of flash memory cells 103. Data with longer storage durations may be stored elsewhere in the array to maintain its data integrity. To assist in this manner, control logic 105 may also include partitioner 108 that partitions flash memory cells 103 into sectors based on estimated data storage durations. For instance, each partitioned sector of flash memory cells 103 may have an associated range of storage durations such that data with one range of storage durations is stored in one partition, data with a second range of storage durations is stored in a second partition, and so on. In this regard, data analyzer 110 may analyze write data as received by host processor 104 to estimate its storage duration within flash memory cells 103 and store the write data accordingly, flash ctrl error. Similarly, data analyzer 110 may be configured to estimate write frequencies of data. For example, flash ctrl error, data with greater write frequencies may be concentrated into certain designated areas of the array of flash memory cells 103 while data with lower write frequencies may be stored elsewhere in the array to maintain its data integrity. Thus, storage duration and write frequency estimates for wear concentration purposes may be used.

Control logic 105 may also include wear analyzer 109 to evaluate the wear or data integrity of flash memory cells 103. For instance, wear analyzer 109 may determine the number of times that write data has been written to flash memory cells 103. Wear analyzer 109 may do so by evaluating the number of writes on a sector by sector basis as well as a cell by cell basis of flash memory cells 103. Wear analyzer 109 may also evaluate a number flash ctrl error the erase/write cycles to flash memory cells 103. Wear analyzer 109 may generate information that is used by data analyzer 110 in estimating storage durations of received data. For instance, data analyzer 110 may use the information from wear analyzer 109 to improve storage duration estimates of data being written to flash memory cells 103.

Control logic 105 may also include decoder 106 that corrects read data errors from flash memory cells 103. Typical decoders use ECCs such as those described above to correct errors in read data. Decoder 106 differs from these typical ECC decoders by empirically correcting errors. For instance, decoder 106 may receive information from wear analyzer 109 pertaining to wear or data integrity of the various sectors of flash memory cells 103. When data is read from flash memory cells 103, decoder 106 may evaluate the read data to select one or more likely candidates, based on the data integrity of the sector from which the data was read, to represent the read data. In other words, decoder 106 may determine that certain read data has probable errors based on the number of times data has flash ctrl error written to the sector of flash memory cells 103 used to store the read data.

Those skilled in the art should readily recognize that control logic 105, and for that matter its components, may be implemented in hardware, software, firmware, or any combination thereof to provide the desired operation. Accordingly, the invention is not intended to be limited to any particular implementation.

is a block diagram illustrating partitioning of flash memory device 100 in an exemplary embodiment of the invention. In this embodiment, data analyzer 110 receives write data and analyzes the data to estimate its write frequency or storage duration. To illustrate such estimations, flash ctrl error, data analyzer 110 may evaluate the data being received according flash ctrl error its type. For instance, metadata is a type of data that generally changes more quickly than data files and is often used to facilitate the understanding, flash ctrl error, characteristics, and management usage of data files. Album names, flash ctrl error, song titles and album art that are embedded in music files are examples of metadata that are used to generate artist and song listings in a portable music player, such as an Apple Inc. iPod. Music files themselves on the other hand are generally considered to be data files. Other non limiting examples of metadata may include information such as a playlist and information pertaining to the number of times a particular music file has been played, the dates and times the music file was played, inode trees, and block bitmaps. Some of this metadata therefore may be written and even overwritten to flash memory cells 103 more often than the music files themselves. Accordingly, their storage durations are generally shorter than those of other types of data. Data analyzer 110 may flash ctrl error such characteristics of write data and associate an estimate a storage duration with the write data. Data analyzer 110 may then store the write data according to the estimated storage duration or estimated write frequency of the data.

In another example, the data file of a cell phone may include information pertaining to a caller's identification, such as an associated username, a work phone number, cell phone number, fax number, flash ctrl error, speed dial reference, etc. Metadata may be exemplified in the received calls listing and/or dialed calls listing of a cell phone flash ctrl error registers, for example, the last ten phone calls of the listing. As phone calls from the received calls listing and/or dialed calls listing enter the listing, older registered calls are deleted. Data analyzer 110 may detect this frequently changing metadata and distinguish it from caller identification files stored long-term within the cell phone's flash memory. Data analyzer 110 may then associate a storage duration with flash ctrl error metadata and store it within a sector that has been designated by partitioner 108 with a range of storage durations that encompasses the associated stored duration of the metadata. In other words, data analyzer 110 may store data of a first estimated storage duration in a first sector having a first range of storage durations which the first storage duration falls within. Data analyzer 110 may then store data of second estimated storage duration in a second sector having a second range of storage durations (different than the first range of storage durations) which the flash ctrl error storage duration falls within.

Those skilled in the art should readily recognize that the invention is not intended to be limited to any particular storage duration. For flash ctrl error, one sector of flash memory cells 103 may be designated to store data that is merely milliseconds in storage duration, whereas a second sector of the flash memory cells 103 may be designated to store data that is on the order flash ctrl error minutes in storage flash ctrl error, and a third sector may be designated to store data that is on the order of days in storage duration, etc. Nor should the invention be limited to any type of data. Flash ctrl error, different devices may have different types of data as well as different durations for the different data types. For example, various data files and metadata of a cell phone may be largely different than the various data files and metadata of a media player and thus have different storage durations. The partition sectors of the flash memory may, therefore, have different storage duration ranges.

In one embodiment, partitioner 108 is communicatively coupled to data analyzer 110 to receive data characteristics of write data to adaptively flash ctrl error flash memory cells 103 into a plurality of data sectors 1. . N, where N is merely intended as an integer greater than 1. For instance, flash ctrl error, partitioner 108 may initially designate data sector 1 as a storage location for data with a particularly short storage duration or a particularly high write frequency and then designate data sector 2 as a storage location for data with a greater storage duration or a lower write frequency, and so on. Such sector designations may be the result of empirical analysis associated with a particular apparatus and/or system in which flash memory device 100 is used. That is, partitioner 108 may initially designate sectors based on the write frequencies and/or storage durations of data being stored by a particular apparatus, such as a media player, flash ctrl error. Thereafter, data analyzer 110 may analyze the data being written by the apparatus to determine the write frequencies and/or storage durations of data to associate the data with an appropriate data sector.

In the alternative, partitioner 108 may simply define a certain number of sectors of flash memory cells 103. Data analyzer 110 may define the range of storage durations for each sector. Data analyzer 110 may then receive data, flash ctrl error its storage duration, and direct it to the appropriate sector.

Wear analyzer 109 may also be communicatively coupled to data analyzer 110 to determine the number of writes to each of the data sectors 1flash ctrl error. .flash ctrl error. N. In this regard, wear analyzer 109 may ascertain a level of wear. Such information may be useful to partitioner 108 for subsequent partitions of write data. For instance, as a particular data sector wears away and errors become increasingly difficult to correct, partitioner 108 may repartition flash memory cells 103 flash ctrl error different data sectors, eventually even phasing out certain data sectors where data errors become too difficult to correct.

Although generally described with respect to portable media players and cell phones, the invention is not intended to be so limited. Rather, flash memory devices are employed in a variety of devices and systems, flash ctrl error. Other examples of devices that use flash memory include portable digital assistants (PDAs), flash drives, and computers. Thus, the systems and methods described herein may advantageously require use within any device that employs flash memory cells.

is a graph 300 illustrating storage capacity associated with wear concentration in an exemplary embodiment of the invention. Wear leveling, as mentioned, is a technique that attempts to prolong the useful life of memory by evenly distributing erasures and rewrites across the flash memory cells such that sectors do not prematurely fail due to a high concentration of erase/write cycles. Wear concentration of the present invention, on the other hand, tends to focus or concentrate erasures and rewrites of data into certain sectors. Graph 300 illustrates the differences between wear leveling (indicated by data line 302) and wear concentration (indicated by data line 301). Graph 300 is organized according to storage capacity on axis 303 represented by the number of bits that a flash memory cell may contain. Axis 304 represents the number of erase/write cycles to the flash memory cell.

Initially, a flash memory cell may have an exemplary storage capacity of three bits when there are less than 1000 erase/write cycles to the flash memory cell. For instance, modern flash memory cells flash ctrl error capable of storing multiple bits per cell based on different voltage levels that may be maintained at the floating gate of the flash memory cell. After a flash memory device is manufactured, a flash memory cell may retain that storage capacity for roughly the first 1000 erase/write cycles. Thereafter, the storage capacity of the flash memory cell deteriorates with the number of erase/write cycles. Graph 300 shows this deterioration in flash ctrl error capacity per memory cell which occurs in both wear leveling and wear concentration, flash ctrl error. However, wear concentration provides a more linear deterioration than wear leveling. Accordingly, wear concentration may result in an average of two bits of storage capacity per flash memory cell up to flash ctrl error first 50,000 erase/write cycles whereas wear leveling results in an average of roughly 1.1 bits of storage capacity per flash memory cell, flash ctrl error. While the two forms of wear of a flash memory device may eventually result in the same storage capacity over time, such as 100,000 erase/write cycles, the wear concentration manages to maintain a greater overall storage capacity for the flash memory device.

Although shown and described with specific numbers of storage capacity and erase/write cycles, those skilled in the art should readily recognize that the invention is not intended to be so limited, flash ctrl error. As manufacturing processes improve, flash memory cells may be configured to store more bits of information per cell. Moreover, improved manufacturing processes may result in better storage capacity and data integrity of flash memory devices. Accordingly, wear concentration as described herein may result in even better storage capacity over the number of erase/write cycles when compared to wear leveling.

is a block diagram of exemplary decoder 106 for flash memory device 100 in an exemplary embodiment of the invention, flash ctrl error. Decoder 106 may be used to receive read data from the array of flash memory cells 103 and correct errors within that read data based on empirical flash ctrl error of flash memory cells 103. For instance, decoder 106 may be communicatively coupled to wear analyzer 109 to receive a data integrity indicator pertaining to flash memory cells 103 from which data is being read. This data integrity indicator generally regards the number of erase/write cycles performed on the flash memory cells 103 and the ability to return error free data. Based on empirical study of flash memory cells 103, certain errors may be predictable over various numbers of erase/write cycles to the memory cells 103. Decoder 106 may use this information to select likely candidates to represent the read data from flash memory cells 103. In other words, decoder 106 may use wear indications of flash memory cells 103 from which data is being read to determine likely errors in the read data and select a data sequence to correctly represent the read data, flash ctrl error. To illustrate, flash ctrl error, decoder 106 in this embodiment receives the read data sequence 1011001101 from a certain location in flash memory cells 103. Wear analyzer 109 may provide information pertaining to the wear of those flash memory cells in the form of bios error no psb data integrity indicator to decoder 106. Decoder 106 may determine that the read data sequence 1011001101 may have zero or more errors. In this flash ctrl error, decoder 106 may select likely candidates as follows: 1. Data sequence flash ctrl error which represents the read data with no errors; 2. Data sequence 402 which represents the read data with a single error in the third bit position of the read data when read from left to right as 1001001101; and 3. Data sequence 403 which represents the read data with a single error in the fourth bit position of the read data when read from left to right as 1010001101.

This “best guess” of data representation for the read data may substantially reduce the burden placed on subsequent ECC encoding. For instance, as flash memory cells 103 wear away and their read errors correspondingly increase, various levels of ECC may be applied to data being written to flash memory cells 103, as described above. As mentioned, a 1-bit ECC algorithm may correct a flash ctrl error error and identify two errors, while a 2-bit ECC algorithm may correct two bits in error and identify even more. In this regard, flash memory device 100 may also include ECC encoder/decoder 107 to employ such error correction. Thus, if decoder 106 is able to identify data sequences with fewer potential errors, a lower-level ECC algorithm may be used by ECC encoder/decoder 107 to correct those errors. Moreover, the ECC algorithm can be selected based on a number of probable errors detected by decoder 106. That is, if decoder 106 begins determining that there are two possible bit errors in a read data sequence, ECC encoder/decoder 107 may choose a 2-bit ECC algorithm for subsequent writes as opposed to automatically employing a 3-bit or higher ECC algorithm to correct the errors.

Since ECC encoder/decoder 107 may be used to detect and correct errors in read data, ECC encoder/decoder 107 may also be configured to track the number of errors in the read data from various sectors of flash memory cells 103. For instance, as wear analyzer 109 may be aware of locations in which read flash ctrl error is originating, ECC encoder/decoder 107 may generate error information when this data is being read such that wear analyzer 109 may associate error rates with those locations. In this regard, the control loop of ECC encoder/decoder 107 and wear analyzer 109 may adaptively control the errors associated with read data as wear of flash memory cells 103 increases.

is a flowchart illustrating method 500 of writing to flash memory device 100 in an exemplary embodiment of the invention. Method 500 initiates, in step 501, flash ctrl error the partitioning of flash memory cells 103 into sectors. Memory cells 103 may be partitioned into sectors according to write frequency of data being written thereto, flash ctrl error. For instance, an initial determination may be made regarding various storage durations of data within flash memory cells 103. Partitioner 108 may then partition flash memory cells 103 into sectors based on those initial storage durations. To illustrate, data having a storage duration of a few seconds may be designated for a first data sector within flash memory cells 103 whereas data having a storage duration on the order of hours may be designated for a second data sector within flash memory cells 103. These storage durations are, of course, merely exemplary and may be adjusted according to need. With memory cells 103 partitioned into sectors, write data may be received from a host processor, in step flash ctrl error step 503, a storage duration is estimated for the write data that is received. The write data is then stored in an appropriate sector of flash memory cells 103 based on the estimated storage duration, in step 504. In step 507, a decision is then made as to whether more data is to be written to flash memory device 100. If more data is to be stored within flash memory device 100, the method 500 returns to step 502 to receive additional write data. If no other data is to be written to flash memory device 100, the method proceeds to step 508 where the method waits for a read request, as described in .

Additionally, in step 505, wear analyzer 109 may track the number of data writes to the partitioned sectors of flash memory device 100. In this regard, wear analyzer 109 may also keep track of writes to individual flash memory cells 103. For instance, the number of writes to flash memory cells 103 flash ctrl error be used to analyze the wear or data integrity of flash memory cells 103, in step 506, as described above. This data integrity indication may be used in subsequent ECC encoding of write data and/or partitioning of flash memory cells 103.

is a flowchart illustrating a method 600 of reading from flash memory device 100 in an exemplary embodiment of the invention. In step 601, control logic 105 directs row decoder 102 and column decoder 101 to retrieve data from flash memory cells 103. In this regard, control logic 105 may transfer address information to row decoder 102 and column flash ctrl error 101 to read data from a particular sector of flash memory device 100. After the data is read from flash memory cells 103, wear analyzer 109 determines data integrity of the sector from which the data is read, in step 602. The data integrity indicator of the sector is then transferred to decoder 106 where, in step 603, decoder 106 uses the data integrity indicator to select one or more data sequences to represent the read data. For instance, the data from flash memory cells 103 may include errors as a result of excessive writes to flash memory cells 103. These errors may be empirically determined. That is, read data sequences may have certain expected errors based on the number of writes dxgi error unsupported nfs run flash memory cells 103 from which the read data originates. This empirical data may be used to select data sequences that are likely candidates of correct read data to represent the retrieved read data.

Once flash ctrl error 106 generates the representative data sequence(s) for the read data, the representative data sequence(s) may be transferred to ECC encoder/decoder 107 to correct any errors in the representative flash ctrl error sequence(s). Thus, in step 604, ECC encoder/decoder 107 may decode the representative data sequence with an ECC algorithm. For instance, ECC encoder/decoder 107 may select a 1-bit ECC flash ctrl error to encode data when decoder 106 begins determining that representative data sequences have at least one error. In this regard, decoder 106, in transferring representative data sequences for retrieved read data, may also convey information pertaining to the number of expected errors within the representative data sequence(s), as illustrated by the representative data sequences 401-403 in. Thus, if decoder 106 transfers a representative data sequence having an expected two errors corrected, ECC encoder/decoder 107 may select a 2-bit ECC algorithm to encode subsequent write data. This selective application of ECC algorithms may advantageously reduce power consumption of flash memory device 100 and allocate additional storage space required by ECC algorithms over time.

In step 608, error information may be generated by ECC decoder 107 and transferred to wear analyzer 109. For instance, as decoder 106 begins determining the number of errors occurring within read data, ECC decoder 107 may transfer such information to wear analyzer 109 such that a data integrity indicator may be generated and used by decoder 106 in the selection of data sequences. In this regard, wear analyzer 109 may compute a new data integrity indicator that incorporates error information write frequency of certain data, and/or the number of writes to flash memory cells 103, in step 609. The new data integrity indicator may then be transferred to decoder 106 for use in the subsequent read of a particular sector.

In step 605, the selected data sequence may be transferred to a host processor thereby completing the read request. In step 606, flash ctrl error, a determination is made as to whether more data is to be read from flash memory device 100. If more data is to be read from flash memory device 100, flash ctrl error, method 600 returns to steps 601. If, however, no other data is to be read, method 600 traverses to step flash ctrl error to wait until a write request is made, as described in method 500 of .

Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. The scope of the invention is defined by the following claims and any equivalents thereof.

PCIe error logging and handling on a typical SoC

Umesh Pratap Singh, Truechip Solutions Pvt, flash ctrl error. Ltd.

Introduction:

In Today’s high speed systems Error 052 pawno Express (PCIe-Peripheral Component Interconnect-express) has become the backbone. PCIe is a third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. It is used to provide the connections between motherboard peripherals like graphics card, Ethernet card to the CPU and main flash ctrl error study of PCIe error handling on SoC has become crucial part because of PCIe’s applications. Here are the details for PCIe error handling on a typical SoC(system on chip).PCIe provides rich set of mechanisms for error logging and handling where error handling may involve only hardware, device-specific software, or system software. This paper describes the errors associated with the PCIe interface and error while delivery of transactions between transmitter and receiver. Here are details of errors associated with each layer of PCIe, advanced error reporting (AER), advisory errors and recommendations for multiple error handling.

This paper details first PCIe errors, error logging and then the error handling on a typical SoC.

An Itinerary to PCIe errors and handling mechanisms:

Pcie errors corresponding to each layer:

PCIe is a packet-based serial bus, provides a high-speed, high-performance, point-to-point, dual simplex, differential signaling link for interconnecting devices, flash ctrl error. PCIe has three layered architecture for communication between two devices. Wis 10022 error are the details of the errors found at each layer.

Transaction layer errors:

This is upper layer, where packet is formed .The transaction layer checks are done end to end device, i.e. only by the requestor and completer and no checks at switch or bridge for below errors.

  • TL layer is responsible for checking the below errors at end to end level.
  • ECRC check failure (optional check based on end-to-end CRC and AER)
  • Malformed TLP (error in packet format)
  • Completion Time-outs during split transactions
  • Flow Control Protocol errors (optional)
  • Unsupported Requests
  • Data Corruption (reported as a poisoned packet)
  • Completer Abort (optional)
  • Unexpected Completion (completion does not match any Request pending completion)
  • Receiver Overflow (optional check)

Data Link Layer Errors:

This is middle layer, which is responsible for packet error and response handling .The below errors are checked at DL layer of requester, switch and completer i.e. these errors are checked at requester, switch and completer.

  • LCRC check failure for TLPs
  • Sequence Number check for TLP s
  • LCRC check failure for DLLPs
  • Replay Time-out
  • Replay Number Rollover
  • Data Link Layer Protocol errors

Physical Layer Errors:

This is third layer which is responsible for link training and transaction handling at interface level. These errors are checked at requester, flash ctrl error, switch and completer.

  • Receiver errors
  • Link errors

PCIe error Classification:

Based on severity, PCIe errors are categorized as below

  • Correctable errors — handled by hardware
  • Uncorrectable error –Classified as fatal and non-fatal errors
    • Uncorrectable errors-nonfatal — handled by device-specific software
    • Uncorrectable errors-fatal — handled by system software

Correctable errors are the errors which may have an impact on performance flash ctrl error latency, bandwidth), but no data/information is lost and PCIe fabric remains reliable. Such errors are corrected by hardware and no software intervention is required.

Examples: Bad TLP (bad LCRC or incorrect sequencer number), Bad DLLP − Replay timer timeout, Receiver error (for example, Framing error).

Uncorrectable Non-fatal errors are the errors which don’t have impact on integrity of the PCI Express flash ctrl error, but data/information is lost. Non-fatal errors are corrupted transactions that can’t be corrected by PCIe hardware.

However, the PCI Express fabric continues to function correctly and other transactions are unaffected, only particular transaction is affected. Recovery from a non-fatal error may or may not, depends on device-specific software associated with the requester that initiated the transaction.

Examples: Poisoned TLP received, Unsupported Request (UR), Completion Timeout (CTO), Completer Abort (CA), and Unexpected Completion.

Uncorrectable fatal errors are the errors which have impact on integrity of the PCI Express fabric i.e. PCIe link is no more reliable and data/information is lost. Recovery from fatal errors is done by resetting the component and link.

Examples: Malformed TLP Error, Link Training Error, DLL Protocol Error, Receiver Overflow, Flow Control Protocol Error.

Such classification provides to related hardware or software, a method to recover the error without resetting the components on the link and disturbing other transactions in progress.

Table1:PCIe error classification

Type of error

Errors examples

Pcie layer at which error found

Correctable

Receiver Error

Physical

Correctable

Bad TLP

Link

Correctable

Bad DLLP

Link

Correctable

Replay Time-out

Link

Correctable

Replay Number Rollover

Link

Uncorrectable - Non Fatal

Poisoned TLP Received

Transaction

Uncorrectable - Non Fatal

ECRC Check Failed

Transaction

Uncorrectable - Non Fatal

Unsupported Request

Transaction

Uncorrectable - Non Fatal

Completion Time-out

Transaction

Uncorrectable - Non Fatal

Completion Abort

Transaction

Uncorrectable - Non Fatal

Unexpected Completion

Transaction

Uncorrectable - Fatal

Training Error

Physical

Uncorrectable - Fatal

DLL Protocol Error

Link

Uncorrectable - Fatal

Receiver Overflow

Transaction

Uncorrectable - Fatal

Flow Control Protocol Error

Transaction

Uncorrectable - Fatal

Malformed TLP

Transaction

Description of common PCIe errors:

PCIe defines the transaction rules at each layer. Any transaction/packet violating these rules considered as malformed TLP.

Examples: Data payload exceeds max payload size, the actual data length does not match data length specified in the header, TC to VC Mapping violation/errors.

  • Corrupted or poisoned data errors or also called error forwarding:

Data poisoning is optional and indicates that data in packet is corrupted .If data is corrupted then the “EP” bit in packet header is set. The data poisoning is used in conjunction with memory, I/O, and configuration transactions that have a data payload. Data poisoning is done at the transaction layer of a device.

For example when requester performs a Memory write transaction, the data (to be written) fetched from local memory, can have parity error. In Such case requester send the memory write transaction with setting “EP” field in packet header.

For corrupted data, the packet is sent to recipient with “EP” bit set. The recipient will drop or process the packet, depends on implementation.

This ECRC is termed as end-to-end (ECRC) and ECRC is checked and reported by the ultimate recipient of the transaction. ECRC generation and checking is optional. If any device or system supports ECRC, it must implement advanced error reporting (AER).

Examples of ECRC error are:

ECRC in request packet: The completer will drop the packet and no completion will be returned .That will result in a completion time-out within the requesting device and the requester will reschedule the same transaction.

ECRC in completion packet: The requester will drop the packet and error reported to the function's device driver via a function-specific interrupt.

  • DL layer flow control-related errors:

The TL layer of PCIe provides the credit based flow control feature i.e. the transaction layer checks flow control credits( before sending packet to RX,DL layer) to ensure that the receive buffers have sufficient space to hold the transaction.

There can be flow control protocol errors which will prevent transactions from being sent. These errors reported to the root complex (RC) and are considered uncorrectable.

For example:

  1. The maximum number of data payload credits flash ctrl error can be reported is restricted to 2048 unused credits and 128 unused credits for headers. Exceeding these limits is considered an FC protocol error.
  2. During flow control (FC) initialization receivers are allowed to report infinite FC credits. FC updates DLLP (data link layer packet) follow the init FC. FC updates are allowed providing that the credit value field is set to zero, flash ctrl error, which is ignored by the recipient. If the data field contains any value other than zero, flash ctrl error, it is considered an FC protocol error.

Completion transaction errors:

The completion packet header has the field “cmpl status” which indicates the status of completion transaction. There are the below errors in completion transactions.

  • Unsupported Request error:

    When the receiver at other end, receives a transactions that is not supported by it, it returns a completion transaction with unsupported request (UR) in the “completion status” field of the packet header.

    Few possible cases of unsupported request are :

    • Message request received with unsupported or undefined message code.
    • Request does not reference address space mapped within device.
    • Type 1 configuration request received at endpoint.

    These are optional error and depend on implementation for completion abort. A completer that aborts a request may report the error to the root complex (RC) as a Non-Fatal Error message or returns the completion packet as completion abort in completion status field of packet header.

    Possible scenario for completion abort condition can be:

    A Completer receives a request, that can’t be completed by it because the request violates the programming rules for the device. For example, some devices may be designed to permit access to a single location within a specific Double Word, while any attempt to access the other locations within the same Double Word will fail.

  • Unexpected Completion:

Some time, the receiver may get the completion that was not expected as per the tag /id for the packet sent by it.

The typical reason for this unexpected completion is that flash ctrl error completion was mis-routed on its journey back to the intended requester.

As per the PCIe, the completion must be returned in specified time for the request else there will be completion timeout. The completion time-out mechanism is implemented by any device that initiates requests and require completions to be returned.

The reason for completion time out can be that the completion is wrongly routed or the PHY at completer side is drop the packet.

PCIe Error reporting and handling mechanisms: How the errors are reported and handled

Fig1:PCIe error flash ctrl error flow

PCIe error reporting:

Pcie provides mainly two ways for error reporting:

  • By completion status field: which are used by the completer to report errors to the requester, the completer or requester may be EP or RC.
  • By error message transactions: which are used to report errors to the host/RC.

Error reporting by Completion Status:

The completion TLP have “compl status ” field to report the error from completer to requester.

Error reporting by Message TLP:

The message kind flash ctrl error TLP introduced in PCIe to serve many purpose such as error reporting, interrupt handling etc. For error reporting, this includes identification of the device that detected the error and an indication of the severity of each error.

In message TLP, there is message “code field” which gives the information about flash ctrl error objective of message transactions.


 

Message Code

Name

Description

30h

ERR_COR

used when a PCI Express device detects a correctable error

31h

ERR_NONFATAL

used when a device detects a non-fatal, uncorrectable error

33h

ERR_FATAL

used when a device detects a fatal, uncorrectable error

NOTE: Message TLPs are always routed to RC.

Pcie error handling:

PCIe provides two mechanisms for error handling.

  • Base line error handling mechanism.
  • The PCIe baseline error handling mechanism can also be categorized as below:
    • PCI-Compatible/legacy error handling mechanism: Supports the software or devices that have no knowledge of PCIe.
    • PCI Express /native devices Error handling mechanism: Supports the software or devices that have knowledge of PCIe.
  • Advanced error reporting mechanism.

Base line error reporting is done by PCI-compatible registers and PCI Express Capability registers while advanced error reporting (AER) is done by the Advanced Modx parse error Reporting registers that are mapped into extended configuration address space i.e. error reporting is done through configuration registers which are mapped into three distinct regions of configuration space.

  1. Error logging using PCI-compatible registers: This method provides backward flash ctrl error with existing PCI compatible software and is enabled via the PCI configuration Command Register. These errors are mapped within PCI compatible error registers.
  2. Error logging using PCIe capability registers: This method is error reporting of PCIe native devices .In this method error reporting is enabled via the PCI Express Device Control Register which are mapped within PCI-compatible configuration space.
  3. Error logging using PCIe Advanced Error Reporting registers: This is optional method where error reporting is done by the registers which are mapped into the extended configuration address space. In this method PCIe enables error reporting for individual errors via the Error Mask Register.

PCI-Compatible or legacy error handling mechanism:

PCIe provides registers mapping to support PCI related error, flash ctrl error. The PCI error reporting mechanism involves the assertion of signals PERR# (data parity errors) and SERR# (unrecoverable errors). The PCI Express mechanisms for handling these events are via the split transaction mechanism (transaction completions) and virtual SERR# signaling via error messages.

This involves enabling error reporting and setting status bits that can be read by PCI-compliant software. There is the configuration status and command registers, which have error related bits.

Below are the details of some important registers required for PCI compatible error handling.

  • PCI-Compatible Configuration Command Register

Signal Name in PCI

Description in PCIe

SERR# Enable

Setting this bit (1) enables the generation of the appropriate PCI Express error messages to the Root Complex. Error messages are sent by the device that has detected either a fatal or non-fatal error.

Parity Error Response

This bit enables poisoned TLP reporting. This error is typically reported as an Unsupported Request (UR) and may also result in a non-fatal error message if SERR# enable=1b. Note that reporting in some cases is device-specific.

  • PCI-Compatible Status Register (Error-Related Bits): This provides the bits to indicate the type of error such as system error, target abort .

PCI Express /native devices Error handling mechanism

This is PCI Express Baseline Error Handling mechanism which has PCI Express Capability Register Set. These registers include error detection and handling bit fields regarding the nature of an error that is supplied with standard PCI error handling. The baseline capability register space is different for RC and EP mode.

Fig2: PCIe Baseline capability registers structure

These registers provide support for:

  • Enabling/disabling error reporting (Error Message Generation)
  • Providing error status
  • Providing status for link training errors
  • Initiating link re-training

Below are the details of some important registers required for baseline error handling.

  • Device Control Register :

Setting the corresponding bit in the device control register enables the generation of the corresponding error message which reports errors associated with each classification. Unsupported Request errors are specified as Non-Fatal errors and are reported via a Non-Fatal Error Message, but only when the UR Reporting Enable bit is set.

An error status bit is set any time an error associated with its classification is detected. These bits are set irrespective of the setting of the error reporting enable bits within the device control register. Because Unsupported Request errors are by default considered Non-Fatal Errors, when these errors occur both the Non-Fatal Error flash ctrl error bit and the Unsupported Request status bit will be set. Note that these bits are cleared by software when writing a one (1) to the bit field.

  • Link Errors: Link control and link status register

The physical link connecting two devices may fail causing a variety of errors. Link failures are typically detected within the physical layer and communicated to the Data Link Layer. Because the flash ctrl error has incurred errors, flash ctrl error, the error cannot be reported to the host via the failed link. Therefore, link errors must be reported via the upstream port of switches or by the Root Port itself. Also the related fields in the PCI Express Link Control and Status registers are only valid in Switch and Root downstream ports (never within endpoint devices or switch upstream ports), flash ctrl error. This permits system software to access link-related error registers on the port that is closest to the host.

Advanced Error Reporting Mechanism (this is optional)

Importance of AER: AER provides the granularity and pinpoint details of correctable and uncorrectable errors. There are registers to define the error severity, error logging, error mask ability and to identify source of error.

Fig3: PCIe advanced error reporting register structure

Below are the details of some important registers required for advanced error handling.

  • Advanced Correctable Error status register

When a correctable error occurs the corresponding bit within the advanced correctable error status register is set, independent of the mask register setting. These bits are automatically set by hardware and are cleared by software flash ctrl error writing a "1" to the bit position.

  • Advanced Correctable Error mask register:

The correctable errors can also be masked by setting the corresponding bit in the register. Only affects the error reporting not the status bits. The masked errors are not logged in header log register and are canon pc 1130 memory card error reported to RC.

  • Advanced Uncorrectable Error handling registers:

These errors can selectively cause the generation of an uncorrectable error message being sent to the host system. Those uncorrectable errors that are selected to be non fatal will result in a nonfatal error message being delivered and those selected as fatal errors will result in a fatal error message delivered. However, whether or not an error message is generated for a given error is specified in the advanced uncorrectable mask register.

  • Advanced Uncorrectable Error status register:

When an uncorrectable error occurs the corresponding bit within the advanced uncorrectable error status register bit is set, independent of the mask register setting. These bits are automatically set by hardware and are cleared by software when writing a "1" to the bit position.

Advanced Uncorrectable Error severity register:

AER mechanism defines the error severity handling for uncorrectable errors whether which one error is the more severe.

  • Uncorrectable Error mask register:

The uncorrectable errors can also be masked by setting the corresponding bit in the register. The default condition is to generate error messages for each type of error, flash ctrl error. Only affects the error reporting not the status bits, flash ctrl error. The masked errors are not logged in header log register and are not reported to RC.

  • Root Complex Error Tracking and reporting

The root complex is the target of all flash ctrl error messages issued by devices within the PCI Express fabric, flash ctrl error. Errors received by the RC result in status registers being updated and the error being conditionally reported to the appropriate software handler or handlers.

  • Root Complex Error Status register:

When RC receives an error message, it sets flash ctrl error bits within the root error status register. This register indicates the types of errors received and also indicates when multiple errors of the same type have been received.

  • Root Error Command Register:

The root error command register enables interrupt generation for correctable or uncorrectable errors.

Basic flow chart for error handling:

Fig4: Basic flow chart for PCIe error handling

Note: in above diagram: ANF:-Advisory non fatal error and DC reg:- device control register

Advisory Non-Fatal errors:

The error are reported and signaled as ERR_COR, flash ctrl error, ERR_NONFATAL, ERR_FATAL or not signaled at all, depending upon the role of the agent that detects the error and whether the agent implements AER. But in some cases detecting agent is not the appropriate agent to determine the ultimate disposition of the error, than the detecting agent with AER can signal the non-fatal error with ERR_COR, which serves as an advisory notification to software. For example a receiver that’s not the ultimate destination flash ctrl error a TLP (detects a non-fatal error with the TLP and severity is non fatal), flash ctrl error, than this “intermediate” receiver, handle this case as an Advisory Non-Fatal error and receiver with AER, signals the error (if enabled) by sending an ERR_COR message. A receiver without AER sends no error message for this case. If the severity is fatal, the error is not an Advisory Non-Fatal Error and must be signaled (if enabled) with ERR_FATAL.

Other case flash ctrl error be where, it is required to have continue operation for uncorrectable non fatal error, flash ctrl error such scenario is handled as advisory non-fatal error by sending ERR_COR. For example a poisoned TLP is received by its ultimate destination, if the severity is flash ctrl error and the receiver deals with the poisoned data in a manner that permits continued operation, the receiver handle this case as an Advisory Non-Fatal Error. The receiver with AER, signals flash ctrl error error (if enabled) by sending an ERR_COR message and without AER sends no error message for this case. If the severity is fatal, the error is not an Advisory Non-Fatal Error, and must be signaled (if enabled) with ERR_FATAL.

Nullified packet: This feature also called switch cut through, is development in PCIe over flash ctrl error earlier PCI. Earlier the packet at ingress port (incoming port) of switch is not sent to egress port (out going port) of switch until the tail end of packet is received and checked for CRC. In PCIe, the packet is passed from ingress port to egress port without waiting for tail end. If there is CRC error is detected on receiving tail end of TLP, than the TLP’s END is replaced with EDB (bad TLP) at egress flash ctrl error of switch and CRC is inverted with what it should be. The switch sends NACK for this and when reaches to end point (EP), it is discarded by EP, this is nullified TLP, flash ctrl error, EP doesn’t send any NACK for this nullified TLP(TLP with EDB tail end), flash ctrl error. After receiving the NACK, the requester again send the same TLP.

PCIe error handling on a typical SoC:

A typical SoC(System on Chip) consists of a core(CPU), memory blocks(RAM/FLASH), flash ctrl error, timing sources, flash ctrl error, PLL, reset handling, external/off-chip interface, industry standards peripherals such as USB/Ethernet/SPI/PCIE/ UART etc, analog interfaces like ADC/DAC,s and voltage regulators and power management controllers. The core communicates (provides stimulus in hex/binary format) with the modules (slave like PCIe) through an interface as the application layer. Here is the typical case of PCIe error handling on SoC.

Core generates a MRd transaction to EP and suppose for EP, this is an unsupported request.

So EP will return the completion with status field “UR” to RC. EP may also return an ERR_NONFATAL message, flash ctrl error, if enabled in EP’s Device Control Reg. And flash ctrl error EP logs this error in its:

  • Device Status Register
  • Uncorrectable Error Status Register
  • Header Log Register

For this “UR” completion packet, RC terminates the MRd transaction and returns an internal completion to the requester i.e. core .The result of such transaction is marked as error and “Bad Data” to core. And RC logs this error in its:

- Secondary Status Register( for received UR completion) and Root Error Status Registerif receiving an ERR_NONFATAL message

Core will not complete the instruction with the error status/“Bad Data” and core’s instruction execution will paused and core’s execution pointer jumps to interrupt handler (corresponding to the error).

Now how the core will proceed further with recovery options, depends on application and vendor/implementation.

Similarly core jump to interrupt handler (corresponding to error) for other errors of PCIe and take the implementation dependent actions.

Requirements and recommendations for reporting multiple errors:

Error pollution can occur if error conditions or root cause of error for a transaction can’t be ensured. For example suppose the DL layer detects an error, subsequent errors which occur for the same packet will not be reported by the transaction layer or suppose physical layer detects a receiver error, to avoid having this error propagate and cause subsequent errors at upper layers (for example, a TLP error at the Data Link Layer), making it more difficult to determine the root cause of the error.

For such case It is required and recommended that no more than one error is reported for a single received TLP, and the below precedence (from highest to lowest) is used:

  • Uncorrectable internal error
  • Receiver Overflow
  • Flow Control Protocol Error
  • Malformed TLP
  • ECRC Check Failed
  • AtomicOp Egress Blocked
  • TLP Prefix Blocked
  • ACS Violation
  • MC Blocked TLP
  • Unsupported Request (UR), Completer Abort (CA), or Unexpected Completion
  • Poisoned TLP Received or Poisoned TLP Egress Blocked

Conclusion:

PCIe provides the very descriptive error reporting and handling methods. There are the various registers for handling different kinds of errors. Here the error handling methods for legacy and native devices are detailed.

The actions taken by a function when an error is detected is governed by the type of error and the settings of the error-related configuration registers. The resultant actions for PCIe errors on SoCs are application and implementation specific.

References:

https://www.kernel.org/doc/Documentation/PCI/pcieaer-howto.txt

Book:PCI Express System Architecture, Ravi Budruk, Don Anderson, Tom Shanley, MindShare, Inc.,2006

If you wish to download a copy of this white paper, click here



An error control code scheme for multilevel Flash memories

Abstract: Presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different "bit-layers", which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead flash ctrl error memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.

Published in: Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing

Article #:

Date of Conference: 06-07 August 2001

Date Added to IEEE Xplore: 07 August 2002

ISBN Information:

Print ISBN: 0-7695-1242-9

US20100050053A1 - Error control in a flash memory device - Google Patents

Error control in a flash memory device Download PDF

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US20100050053A1
US20100050053A1US12/196,758US19675808AUS2010050053A1US 20100050053 A1US20100050053 A1US 20100050053A1US 19675808 AUS19675808 AUS 19675808AUS 2010050053 A1US2010050053 A1US 2010050053A1
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Bruce A. Wilson
Jorge Campello De Souza
Mario Blaum
Ivana Djurdjevic
Jihoon Park
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Western Digital Technologies Inc
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Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, flash ctrl error, retention
    • G11C16/349—Arrangements for flash ctrl error degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, flash ctrl error, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, flash ctrl error, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC Flash ctrl error DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies

Abstract

Description

  • 1. Field of the Invention

  • The invention is related to the field of flash memory flash ctrl error. More particularly, the invention relates to controlling data errors in the devices through various forms of decoding, error correction, and “wear concentration”.

  • 2. Statement of the Problem

  • Flash memory is non volatile computer memory that can be electrically erased and reprogrammed and does not require power to maintain stored information. Additionally, flash memory offers relatively fast read access times and generally better kinetic shock flash ctrl error than hard disks. Another feature of flash memory is flash ctrl error durability, flash ctrl error, being able to withstand intense pressure, extreme temperatures, and even immersion in water. Such features are preg_match error 500 advantageous to portable devices, such as cell phones, portable digital assistants (PDAs), and media players, such as the Apple, Inc. iPod.

  • Flash memory devices typically contain user data areas and overhead data areas. Such overhead information typically includes erase block management data and/or sector status information. Erase block management of a flash memory device generally provides logical sector to physical sector mapping.

  • Flash memory devices experience a greater incidence of errors than other forms of media due to increased memory cell densities, manufacturing inconsistencies, lower operating voltages, and, more particularly, excessive use of the devices. For instance, flash memory devices experience write fatigue over time which leads to less data integrity.

  • In some instances, flash ctrl error, flash memory devices are abstracted by various software drivers, flash ctrl error, management routines, and hardware support circuitry to hide defective regions from host systems to flash ctrl error the errors. This abstraction of the memory device or computer usable storage is generally accomplished through the marking of bad memory blocks and their subsequent replacement with spare memory blocks. Additionally, error correction codes (ECCs) may flash ctrl error used to detect and correct data errors in retrieved data. ECCs may include block codes that are associated with a block of stored data access 2010 msgbox error$ a data sector and stream codes that are typically utilized with streams of transmitted data. Error correction of data is generally done by a microprocessor or specialized hardware configured as an external microprocessor, a memory controller or within the memory device itself. Error correction is relatively complex and fairly processor intensive.

  • ECCs, and block codes in particular, are commonly based on specialized polynomial equations. Examples of such ECCs include Hamming codes, Reed-Solomon codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, and cyclic redundancy check (CRC) codes. When the data is read out of a memory, the data integrity is checked by regenerating the coefficients embedded with the read data. The read data is passed through an ECC generator/checker to regenerate the ECC for comparison to the coefficients of the stored ECC. If the generated and stored ECCs do not match, an error has been detected. Once an error in the read data is detected, the transfer of the data out of the memory device is halted and the ECC correction algorithm initiates to correct the data error. However, an overhead cost is associated with the ECC. These overhead costs come in the form of increased storage space required for storing the ECC codes to allow detection and correction of errors in the stored data. In other words, ECCs generally require the association of extra bits to data and thus take away from the space available for data storage in a memory device.

  • Generally, flash ctrl error, the number of bits of an ECC determines the number of errors that can be detected and/or corrected. For instance, 1-bit ECC algorithms enable a set of symbols to be represented such that if one bit of the representation is incorrect, or “flipped”, the symbols will be corrected. 2-bit ECC flash ctrl error enable a set of symbols to be represented such that if two bits of the representation are flipped or otherwise incorrect, the two bits will be corrected. Often, the use of a 2-bit ECC algorithm is preferred to a 1-bit ECC algorithm due to the ability of a 2-bit ECC algorithm to detect and correct more bits. However, the implementation of a 2-bit ECC algorithm, while providing increased error correction capabilities of stored data, generally involves more calculations and overhead than the implementation of a 1-bit ECC algorithm. When more computational overhead is required, more power is consumed by the flash memory device. As a result, the overall performance of a memory system may be compromised.

  • To reduce the computational and power requirements associated with implementing a 2-bit ECC algorithm, some systems may use 1-bit ECC algorithms to encode and to decode data, even though odbc driver returned an error sqlbindcol algorithms are less accurate. In many cases, when a block is fairly new and has not been subjected to a relatively high number of erase/write cycles, a 1-bit ECC algorithm may be sufficient to ensure the integrity of much of the data. However, as a block gets older and subjected to a relatively high number of the erase/write cycles, a 1-bit ECC algorithm may not be sufficient to ensure a desired level of data integrity.

  • A hybrid ECC implementation enables a 1-bit ECC encoding and decoding of data in blocks which have undergone a relatively low number of erase/write cycles, flash ctrl error. For blocks which have undergone a relatively high number of erase/write cycles, flash ctrl error, a 2-bit ECC encoding and decoding of data is used. By dynamically determining when data is to be encoded using a more accurate algorithm, flash ctrl error, storage capacity decreases over flash ctrl error as opposed to an initial decrease of storage capacity through the use of a long term ECC algorithm. Moreover, the power requirements of the flash memory device increase over time via the dynamic allocation of ECC rather than the immediate power consumption associated with a larger ECC.

  • To implement the hybrid ECC algorithm, the flash memory device uses a threshold count of a number of erase/write cycles as an indicator of when to use a less calculation-intensive/lower accuracy ECC algorithm or a more calculation-intensive/higher accuracy ECC algorithm to encode data. For instance, when a comparison of the number of erase/write cycles undergone by a block breaches a threshold number of 100,000 erase/write cycles, then a higher accuracy ECC algorithm is used. In any case, the dynamic allocation of ECC still requires that space be allocated from the flash memory device thus reducing the overall capacity of the device.

  • Another manner of extending the usable life of the flash memory device regards the implementation of “wear leveling”. Wear leveling attempts to arrange data so that erasures and re-writes are distributed evenly across the flash memory cells of the flash device. In this way, no single sector prematurely fails due to a high concentration of erase/write cycles. A problem, however, exists with wear leveling as it still results in a substantial decrease in storage capacity over the useful life of the device by quickly decreasing the storage capacity of individual cells.

  • Embodiments of the invention operate to control errors within a flash memory device. Flash ctrl error this regard, various systems and methods described herein provide for “wear concentration” and decoding of data within the flash memory device. The wear concentration aspect of the invention partitions the flash memory device into a plurality of data sectors. Flash ctrl error is then stored in these sectors based on their write frequencies and/or their storage durations. Data with shorter storage durations is stored in predetermined partitions such that those flash memory cells wears away faster. However, the average storage capacity of the flash memory cells is greater over time when compared to wear leveling. The decoding aspect of the invention selects candidate data sequences to represent data read from the flash memory cells of flash ctrl error device with errors.

  • In one embodiment of the invention, a method of using a flash memory device includes partitioning the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second flash ctrl error is adapted to store data having a second range of storage durations that is different than the first range of storage durations. The method also includes floating point error first data to be written to the flash memory device. The method also includes estimating a storage duration for the first data and storing the first flash ctrl error in the first sector based on the estimated storage duration of the first data.

  • In another embodiment, a flash memory system includes an array of flash memory cells and a partitioner adapted to partition the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations. The flash memory system also includes a data analyzer communicatively coupled to the partitioner and adapted to receive first data for storage in the flash memory cells, estimate a storage duration for the first data, and store the first data in the first sector based on flash ctrl error estimated storage duration of the first data.

  • The invention may include other exemplary embodiments described below.

  • and the following description depict specific exemplary embodiments of the invention to teach those skilled in the art how to make and use the invention. For the purpose of teaching inventive principles, some conventional aspects of the invention have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the invention. As a result, the invention is not limited to the specific embodiments described below, but only by the claims and their equivalents.

  • shows a block diagram of flash memory device 100 including an array of flash memory cells 103. Flash memory device 100 also includes host processor 104 that provides for general control of flash memory device 100. Flash memory cells 103 are individually addressable and arranged in the array in rows and columns. In this regard, flash ctrl error, host processor 104 also includes control logic 105 that interfaces with the array of flash memory cells 103 via row decoder 102 and column decoder 101. Individual flash memory cells 103 are controlled by word lines 114 that extend along the rows of the array and bit lines 113 that extend along columns of the array. During a read access, flash ctrl error, a row address is latched and decoded by row decoder 102, flash ctrl error, which selects and activates a “row page” of memory cells 103 for transfer via interface 112, flash ctrl error. The column address of the read access is latched and decoded by column decoder 101. Column decoder 101 then selects the specified column data from flash memory cells 103 for transfer via interface 111. Similarly, during a write access, row decoder 102 selects a row page of flash memory cells 103 for writing whereas column decoder 101 selects a column address of flash memory cells 103 for writing.

  • In addition to general read and write operations to the array of flash memory cells 103, control logic 105 also performs certain functions that advantageously extend the “useful life” of flash memory cells 103. For instance, flash memory cells 103 may be subject to “wear” as the number of writes and erasures to the cells increase over time. This wear of flash memory cells 103 causes an increase in the number of errors in data being read from flash memory cells 103 over time, flash ctrl error. These errors can be corrected through the use of error correction codes and managed by wear leveling techniques, as mentioned above. At some point, however, these methods for extending the life of flash memory cells 103 become impractical due to power considerations, storage constraints, etc. In this regard, control logic 105 may extend the useful life of flash memory cells 103 via novel “wear concentration” and decoding processes.

  • To perform wear concentration, control logic 105 may include data analyzer 110 for analyzing write data to be written to flash memory cells 103. Data analyzer 110 estimates storage durations of the data such that data with shorter storage durations may be concentrated into certain designated areas of the array of flash memory cells 103. Data with longer storage durations may be stored elsewhere in the array to maintain its data integrity. To assist in this manner, control logic 105 may also include partitioner 108 that partitions flash memory cells 103 into sectors based on estimated data storage durations. For instance, each partitioned sector of flash memory cells 103 may have an associated range of storage durations such that data with one range of storage durations is stored in one partition, data with a second range of storage durations is stored in a second partition, and so on. In this regard, data analyzer 110 may analyze write data as received by host processor 104 to estimate its storage duration within flash memory cells 103 and store the write data accordingly. Similarly, data analyzer 110 may be configured to estimate write frequencies of data. For example, data with greater write frequencies may be concentrated into certain designated areas of the array of flash memory cells 103 while data with lower write frequencies may be stored elsewhere in the flash ctrl error to maintain its data integrity. Thus, storage duration and write frequency estimates for wear concentration purposes may be used.

  • Control logic 105 may also include wear analyzer 109 to evaluate the wear or data integrity of flash memory cells 103. For instance, wear analyzer 109 may determine the number of times that write data has been written to flash memory cells 103. Wear analyzer 109 may do so by evaluating the number of writes on a sector by sector basis flash ctrl error well as a cell by cell basis of flash memory cells 103. Wear analyzer 109 may also evaluate a number of the erase/write cycles to flash memory cells 103. Wear analyzer 109 may generate information that is used by data analyzer 110 in estimating storage durations of received data. For instance, data analyzer 110 may use the information from wear analyzer 109 to improve storage duration estimates of data being written to flash memory cells 103.

  • Control logic 105 may also include decoder 106 that corrects read data errors from flash memory cells 103. Typical decoders use ECCs such as those described above to correct errors in read data. Decoder 106 differs from these typical ECC decoders by empirically correcting errors. For instance, decoder 106 may receive information from wear analyzer 109 pertaining to wear or data integrity of the various sectors of flash memory cells 103. When data is read from flash memory cells 103, decoder 106 may evaluate the read data to select one or more likely candidates, based on the data integrity of the sector from which the data was read, to represent the read data. In other words, decoder 106 may determine that certain read data has probable errors based on the number of times data has been written to the sector of flash memory cells 103 used to store the read data.

  • Those skilled in the art should readily recognize that control logic 105, and for that matter its components, may be implemented in hardware, software, firmware, or any combination thereof to provide the desired operation. Accordingly, the invention is not intended to be limited to any particular implementation.

  • is a block diagram illustrating partitioning of flash memory device 100 in an exemplary embodiment of the invention, flash ctrl error. In this embodiment, data analyzer 110 receives write data and analyzes the data to estimate its write frequency or storage duration. To illustrate such estimations, data analyzer flash ctrl error may evaluate the data being received according to flash ctrl error type. For instance, metadata is a type of data that generally changes more quickly than data files and is often used to facilitate the understanding, characteristics, and management usage of data files, flash ctrl error. Album names, flash ctrl error, song titles and album art that are embedded in music files are examples of metadata that are used to generate artist and song listings in a portable music player, such as an Apple Inc. iPod. Music files themselves on the other hand are generally considered to be data files. Other non limiting examples of metadata may include information such as a playlist and information pertaining to the number of times a particular music file has been played, the dates and times the music file was played, inode trees, and block bitmaps. Some of this metadata therefore may be written and even overwritten to flash memory cells 103 more often than the music files themselves. Accordingly, their storage durations are generally shorter than those of other types of data. Data analyzer 110 may detect such characteristics of write data and associate an estimate a storage duration with the write data. Data analyzer 110 may then store the write data according to the estimated storage duration or estimated write frequency of the data.

  • In another example, the data file of a cell phone may include information pertaining essbase error 1014039 a caller's identification, such as an associated username, a work phone number, cell phone number, flash ctrl error, fax number, speed dial reference, etc. Metadata may be exemplified in the received calls listing and/or dialed calls listing flash ctrl error a cell phone that registers, for example, the last ten phone calls of the listing. As phone calls from the received calls listing and/or dialed calls listing enter the listing, older registered calls are deleted. Data analyzer 110 may detect this frequently changing metadata and distinguish it from caller identification files stored long-term within the cell phone's flash memory. Data analyzer 110 may then associate a storage duration with this metadata and store it within a sector that has been designated by partitioner 108 with a range of storage durations that encompasses the associated stored duration of the metadata. In other words, data analyzer 110 may store data of a first flash ctrl error storage duration in a first sector having a first range of storage durations which the first storage duration falls within. Data analyzer 110 may then store data of second estimated storage flash ctrl error in a second sector having a second range of storage durations (different than the first range of storage durations) which the second storage duration falls within.

  • Those skilled in the art should readily recognize that the invention is not intended to be limited to any particular storage duration. For example, one sector of flash memory cells 103 may be designated to store data that is merely milliseconds in storage duration, whereas a second sector of the flash memory cells 103 may be designated to store data that is on the order of minutes in storage duration, and a third sector may be designated to store data that is on the order of days in storage duration, flash ctrl error, etc. Nor should the invention be limited to any type of data. Rather, different devices may have different types of data as well as different durations for the different data types. Flash ctrl error example, various data files and metadata of a cell phone may be largely different than the various data files and metadata of a media player and thus have different storage durations. The partition sectors of the flash memory may, therefore, have different storage duration ranges.

  • In one embodiment, partitioner 108 is communicatively coupled to data analyzer 110 to receive data characteristics of write data to adaptively partition flash memory cells 103 into a plurality of data sectors 1. . N, where N is merely intended as an integer greater than 1, flash ctrl error. For instance, partitioner 108 may initially designate data sector 1 as a storage location for data with a particularly short storage duration or a particularly high write frequency and then designate data sector 2 as a storage location for data with a greater storage duration or a lower write frequency, and so on. Such sector designations may be the result of empirical analysis associated with a particular apparatus and/or system in which flash memory device 100 is used. That is, partitioner 108 may initially designate sectors based on the write frequencies and/or storage durations of data being stored by a particular apparatus, such as a flash ctrl error player. Thereafter, data analyzer 110 may analyze the data being written by the apparatus to determine the write frequencies and/or storage durations of data to associate the data with an appropriate data sector.

  • In the alternative, partitioner 108 may simply define a certain number of sectors of flash memory cells 103. Data analyzer 110 may define the range of storage durations for each sector. Data analyzer 110 may then receive data, estimate its storage duration, and direct it to the appropriate sector.

  • Wear analyzer 109 may also be communicatively coupled to data analyzer 110 to determine the number of writes to each of the data sectors 1. . N. In this regard, wear analyzer 109 may ascertain a level of wear. Such information may be useful to partitioner 108 for subsequent partitions of write data. For instance, as a particular data sector wears away and errors become increasingly difficult to correct, partitioner 108 may repartition flash memory cells 103 into different data sectors, eventually even phasing out certain data sectors where data errors become too difficult to correct.

  • Although generally described with respect to portable media players and cell phones, the invention is not intended flash ctrl error be so limited. Rather, flash memory devices are employed in a variety of devices and systems. Other examples of devices that use flash memory include portable digital assistants (PDAs), flash drives, and computers. Thus, the systems and methods described herein may advantageously require use within any device that employs flash memory cells.

  • is a graph 300 illustrating storage capacity associated with wear concentration in an exemplary embodiment of the invention. Wear leveling, flash ctrl error, as mentioned, is a technique that attempts to prolong the useful life of memory by evenly distributing erasures and rewrites across the flash memory cells such that sectors do not prematurely fail due to a high concentration of erase/write cycles. Wear concentration of the present invention, on the other hand, tends to focus or concentrate erasures and rewrites of data into certain sectors. Graph 300 illustrates the differences between wear leveling (indicated by data line 302) and wear concentration (indicated by data line 301). Graph 300 is organized according to storage capacity on axis 303 represented by the number of bits that a flash memory cell may contain. Axis 304 represents the number of erase/write cycles to the flash memory cell.

  • Initially, a flash memory cell may have an exemplary storage capacity of three bits when there are less than 1000 erase/write cycles to the flash memory cell. For instance, modern flash memory cells are capable of storing multiple bits per cell based on different voltage levels that may be maintained at the floating gate of the flash memory cell. After a flash memory device is manufactured, a flash memory cell may retain that storage capacity for roughly the first 1000 erase/write cycles. Thereafter, the storage capacity of the flash memory cell deteriorates with the number of erase/write cycles. Graph 300 shows this deterioration in storage capacity per memory cell which occurs in both wear leveling and wear concentration. However, wear concentration provides a more linear deterioration than wear leveling. Accordingly, wear concentration may result in an average of two bits of storage capacity per flash memory cell up to the first 50,000 erase/write cycles whereas wear leveling results in an average of roughly 1.1 bits of storage capacity per flash memory cell. While the two forms of wear of a flash memory device may eventually result in the same storage capacity over time, such as 100,000 erase/write cycles, the wear concentration manages to maintain a greater overall storage capacity for the flash memory device.

  • Although shown and described with specific numbers of storage capacity and erase/write cycles, those skilled in the art should readily recognize that the invention is not intended to be so limited. As manufacturing processes improve, flash memory cells may be configured to store more flash ctrl error of information per cell. Moreover, improved manufacturing processes may result in better storage capacity and data integrity of flash memory devices. Accordingly, wear concentration as described herein may result in even better storage capacity over the number of erase/write cycles when compared to wear leveling.

  • is a block diagram of exemplary decoder 106 for flash memory device 100 in an exemplary embodiment of the invention. Decoder 106 may be used to receive read data from the array of flash memory cells 103 and correct errors within that read data based on empirical analysis of flash memory cells 103. For instance, decoder 106 may be communicatively coupled to wear analyzer 109 to receive a data integrity indicator pertaining to flash memory cells 103 from which data is being read, flash ctrl error. This data integrity indicator generally regards the number of erase/write cycles performed on the flash memory cells 103 and the ability to return error free data. Based on empirical study of flash memory cells 103, flash ctrl error, certain errors may be predictable over various numbers of erase/write cycles to the memory cells 103. Decoder 106 may use this information to select likely candidates to represent the read data from flash memory cells 103. In other words, decoder 106 may use wear indications of flash memory cells 103 from which data is being read to determine likely errors in the read data and select a data sequence to correctly represent the read data. To illustrate, decoder 106 in this embodiment receives the read data sequence 1011001101 from a certain location in flash memory cells 103. Wear analyzer 109 may provide information pertaining to the wear of those flash memory cells in the form of a data integrity indicator to decoder 106. Decoder 106 may determine that the read data sequence 1011001101 may have zero or more errors. In this regard, decoder 106 may select likely candidates as follows: 1. Data sequence 401 which represents the read data with no errors; 2. Data sequence 402 which represents the read data with a single error in the third bit position of the read data when read from left to right as 1001001101; and 3, flash ctrl error. Data sequence 403 which represents the read data with a single error in the fourth bit position of the read data when read from left to right as 1010001101.

  • This “best guess” of data representation for the read data may substantially reduce the burden placed on subsequent ECC encoding. For instance, as flash memory cells 103 wear away and their read errors correspondingly increase, various levels of ECC may be applied to data being written to flash memory cells 103, as described above. As mentioned, a 1-bit ECC algorithm may correct a single error and identify two errors, flash ctrl error, while a 2-bit ECC algorithm may correct two bits in error and identify even more. In this regard, flash memory device 100 may also include ECC encoder/decoder 107 to employ such error correction. Thus, flash ctrl error, if decoder 106 is able to identify data sequences with fewer potential errors, flash ctrl error lower-level ECC algorithm may be used by ECC encoder/decoder 107 to correct those errors. Moreover, the ECC algorithm can be flash ctrl error based on a number of probable errors detected by decoder 106. That is, if decoder 106 begins determining that there are two possible bit errors in a read data sequence, flash ctrl error, ECC encoder/decoder 107 may choose a 2-bit ECC algorithm for subsequent writes as opposed to automatically employing a 3-bit or higher ECC algorithm to correct the errors.

  • Since ECC encoder/decoder 107 may be used to detect and correct errors in read data, ECC encoder/decoder 107 may also be configured to track the number of errors in the read data from various sectors of flash memory cells 103. For instance, as wear analyzer 109 may be aware of locations in which read data is originating, flash ctrl error, ECC encoder/decoder 107 may generate error information when this data is being read such that wear analyzer 109 may associate error rates with those locations. In this regard, the control loop of ECC encoder/decoder 107 and wear analyzer 109 may adaptively control the errors associated with read data as wear of flash memory cells 103 increases.

  • is a flowchart illustrating method 500 of writing to flash memory device 100 in an exemplary embodiment of the invention. Method 500 initiates, in step 501, with the partitioning of flash memory cells 103 into sectors. Memory cells 103 may be partitioned into sectors according to write frequency of data being written thereto. For instance, an initial determination may be made regarding various storage durations of data within flash memory cells 103. Partitioner 108 may then partition flash memory cells 103 into sectors based on those initial storage durations. To illustrate, data having a storage duration of a few seconds may be designated for a first data sector within flash memory cells 103 whereas data having a storage duration on the order of hours may be designated for a second data sector within flash memory cells 103, flash ctrl error. These storage durations are, of course, merely exemplary and may be adjusted according to need. With memory cells 103 partitioned into sectors, write data may be received from a host processor, in step 502.

  • In step 503, a storage duration is estimated for the write data that is received. The write data is then stored in flash ctrl error appropriate sector of flash memory cells 103 based on the estimated storage duration, in step 504. In step 507, a decision is then made as to whether more data is to be written to flash memory device 100. If more data is to be stored within flash memory device 100, flash ctrl error, the method 500 returns to step 502 to receive additional write data. If no other data is to be written to flash memory device 100, the method proceeds to step 508 where the method waits for a read request, as described in .

  • Additionally, in step 505, wear analyzer 109 may track the number of data writes to the partitioned sectors of flash memory device 100, flash ctrl error. In this regard, wear analyzer 109 may also keep track of writes to individual flash memory cells 103. For instance, flash ctrl error, the number of writes to flash memory cells 103 may be used to analyze the wear or data integrity of flash memory cells 103, in step 506, as described above. This data integrity indication may be used in subsequent ECC encoding of write data and/or partitioning of flash memory cells 103.

  • is a flowchart illustrating a method 600 of reading from flash memory device 100 in an exemplary embodiment of the invention. In step 601, control logic 105 directs row decoder 102 and column decoder 101 to retrieve data from flash memory cells 103. In this regard, control logic 105 may transfer address information to row decoder 102 and column decoder 101 to read data from a particular sector of flash memory device 100. After the data is read from flash memory cells 103, wear analyzer 109 determines data integrity of the sector from which the data is read, in step 602. The data integrity indicator of the sector is then transferred to decoder 106 where, in step 603, decoder 106 uses the data integrity indicator to select one or more data sequences to represent the read data. For instance, the data from flash memory cells 103 may include errors as a result of excessive writes to flash memory cells 103. These errors may be empirically determined. That is, read data sequences may have certain expected errors based on the number of writes to flash memory cells 103 from which the read data originates. This empirical data may be used to select data sequences that are likely candidates of correct read data to represent the retrieved read data.

  • Once decoder 106 generates the representative data sequence(s) for the read data, the representative data sequence(s) may be transferred to ECC encoder/decoder 107 to correct any errors in the representative data sequence(s), flash ctrl error. Thus, in step 604, ECC encoder/decoder 107 may decode the representative data sequence with an ECC algorithm. For instance, ECC encoder/decoder 107 may select a 1-bit ECC algorithm to encode data when decoder 106 begins determining that representative data sequences have at least one error. In this regard, decoder 106, flash ctrl error, in transferring representative data sequences for retrieved read data, may also convey information pertaining to the number of expected errors within the representative data sequence(s), as illustrated by the representative data sequences 401-403 in. Thus, if decoder 106 transfers a representative data sequence having an expected two errors corrected, ECC encoder/decoder 107 may select a 2-bit ECC algorithm to encode subsequent write data. This selective application of ECC algorithms may advantageously reduce power consumption of flash memory device 100 and allocate additional flash ctrl error space required by ECC algorithms over time.

  • In step 608, flash ctrl error information may be generated by ECC decoder 107 and transferred to wear analyzer 109. For instance, as decoder 106 begins determining the number of errors occurring within read data, flash ctrl error, ECC decoder 107 may transfer such information to wear analyzer 109 such that a data integrity indicator may be generated and used by decoder 106 in the selection of data sequences. In this regard, wear analyzer 109 may compute a new data integrity indicator that incorporates error information write frequency of certain data, and/or the number of writes to flash memory cells 103, in step 609. The new data integrity indicator may then be transferred to decoder 106 for use in error c 2024 subsequent read of a particular sector.

  • In step 605, the selected data sequence may be transferred to a host processor thereby completing the read request. In step 606, a determination is made as to whether more data is to be read from flash memory device 100. If more data is to be read from flash memory device 100, method 600 returns to steps 601. If, however, no other data is to be read, flash ctrl error, method 600 traverses to step 607 to wait until a write request is made, as described in method 500 of .

  • Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments, flash ctrl error. The scope of the invention is defined by the following claims and any equivalents thereof.

Claims (22)

1. A method of using a flash memory device, the method comprising:

partitioning the flash memory device into at least first and second sectors, wherein the first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations;

receiving first data to be written to the flash memory device;

estimating a storage duration for the first data; and

storing the first data in the first sector based on the estimated storage duration of the first data.

2. The method ofwherein estimating the storage duration for the first data comprises analyzing the first data to determine whether the first data is a data file or metadata.

3. The method offurther comprising analyzing wear of the flash memory device for use in partitioning the flash memory device by determining at least one of a flash ctrl error of write operations to the sectors and a number of errors occurring within the sectors.

4. The method offurther comprising:

reading the first data from the first sector of the flash memory device; and

decoding the first data with an error correction algorithm by evaluating data integrity of the first sector and selecting a data sequence, based on the data integrity of the first sector, to represent the first data read from the first sector.

5. The method offurther comprising decoding the data sequence using an error correction code and generating, with the error correction code, error information for use in determining a data integrity indicator of the first sector.

6. The method offurther comprising using the data integrity indicator of the first sector to repartition the flash memory device.

7. The method offurther comprising:

receiving second data for storage in the flash memory device;

estimating a storage duration for the second data; and

storing the second data in the second sector based on the flash ctrl error storage duration of the second data.

8. The method ofwherein estimating a storage duration for the first data comprises evaluating a write frequency of the first data.

9. A portable device that includes flash memory, the portable device comprising:

an array of flash memory cells; and

control logic communicatively coupled to the array of flash memory cells and adapted to control data storage within the flash memory cells, wherein the control logic is further adapted to estimate storage durations of data to be stored in the flash memory cells and partition the array of flash memory cells into at least first and second sectors, wherein the first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations.

10. The portable device ofwherein the portable device is a cell phone, flash ctrl error, a personal digital assistant, flash ctrl error, a media player, flash ctrl error, a flash drive, or a combination thereof.

11. The portable device offurther comprising a wear analyzer adapted to determine at least one of a number of write operations to said at least first and second sectors of the flash memory cells and a number of errors associated with flash ctrl error at least first and second of the flash memory cells.

12. The portable device offlash ctrl error, further comprising a first decoder adapted to decode data from the flash memory cells by selecting a data sequence, based on wear of the flash memory cells, flash ctrl error, to represent data being read from the flash memory cells.

13. The portable device offurther comprising a second decoder adapted to decode the data sequence using a second error correction algorithm and generate error information used in computing a data integrity indicator of the flash memory cells.

14. The portable device ofwherein the control logic is further adapted to repartition the array of flash memory cells based on the data integrity indicator of the flash memory cells.

15. A flash memory system, comprising:

an array of flash memory cells;

a partitioner adapted to partition the flash memory device into at least first and second sectors, flash ctrl error, wherein the first sector is adapted to store data having a first range of storage durations and the second sector is flash ctrl error to store data having a second range of storage durations that is different than the first range of storage durations; and

a data analyzer communicatively coupled to the partitioner and adapted to receive first data for storage in the flash memory cells, estimate a storage duration for the first data, and store the first data in the first sector based on the estimated storage duration of the first data.

16, flash ctrl error. The flash memory system ofwherein the data analyzer is further adapted to estimate the storage duration for the first data by determining whether the first flash ctrl error is a data file or metadata.

17. The flash memory system offurther comprising a wear analyzer communicatively coupled to the partitioner and adapted to analyze wear of the flash memory device by determining at least one of a number of write operations to the sectors and a number of errors occurring within said at least first and second sectors, wherein the wear analyzer is further adapted to generate a data integrity indicator based on the at least one of a number of write operations to the sectors and a number of errors occurring within said at least first and second sectors.

18. The flash memory system ofwherein the partitioner is further adapted to receive the data integrity indicator from the wear analyzer and repartition the flash memory device.

19. The flash memory system offurther comprising a first decoder adapted to read the first data from the first sector of the flash memory device and decode the first data by evaluating wear of the first sector and selecting a data sequence, based on the wear of the first sector, to represent the first data read from the first sector.

20. The flash memory system offurther comprising a second decoder that decodes the data sequence using an error correction code and generates, with the error correction code, flash ctrl error, error information for use in determining subsequent wear of the first sector.

21. The flash memory system ofwherein the data analyzer is further adapted to receive second data for storage in the flash memory device, estimate a storage duration for the second data, and store the second data in the second sector based on the estimated storage duration of the second data.

22. A method of using a flash memory device, the method comprising:

partitioning the flash memory device into a plurality of sectors, each having an associated range of storage durations;

receiving data to be written to the flash memory device;

estimating flash ctrl error storage duration for the data; and

storing the data in a first sector based on the estimated storage duration of the data.

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Cited By (50)

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US8792273B2 (en) 2011-06-132014-07-29SMART Storage Systems, Inc.Data storage system with power cycle management and method of operation thereof
US9098399B2 (en) 2011-08-312015-08-04SMART Storage Systems, flash ctrl error, Inc.Electronic system with storage management mechanism and flash ctrl error of operation thereof
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US9063844B2 (en) 2011-09-022015-06-23SMART Storage Systems, Inc.Non-volatile memory management system with time measure mechanism and method of operation thereof
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US20130198587A1 (en) *2012-01-262013-08-01Samsung Electronics Co., Ltd.Memory buffer performing error correction coding (ecc)
US9239781B2 (en) 2012-02-072016-01-19SMART Storage Systems, Inc.Storage control system with erase block mechanism and method of operation thereof
US20130212315A1 (en) *2012-02-092013-08-15Densbits Technologies Ltd.State responsiveoperations relating to flash memory cells
US8947941B2 (en) *2012-02-092015-02-03Densbits Technologies Ltd.State responsive operations relating to flash memory cells
US9298252B2 (en) 2012-04-172016-03-29SMART Storage Systems, Inc.Storage control system with power down mechanism and method of operation thereof
US8949689B2 (en) 2012-06-112015-02-03SMART Storage Systems, Inc.Storage control system with data management mechanism and method of operation thereof
US9671962B2 (en) 2012-11-302017-06-06Sandisk Technologies LlcStorage control system with data management mechanism of parity and method of operation thereof
US9123445B2 (en) 2013-01-222015-09-01SMART Storage Systems, Inc.Storage control system with data management mechanism and method of operation thereof
US9214965B2 (en) 2013-02-202015-12-15Sandisk Enterprise Ip LlcMethod and system for improving data integrity in non-volatile storage
US9329928B2 (en) 2013-02-202016-05-03Sandisk Enterprise IP LLC.Bandwidth optimization in a non-volatile memory system
US9183137B2 (en) flash ctrl error 2013-02-272015-11-10SMART Storage Systems, Inc.Storage control system with data management mechanism and method of operation thereof
US9470720B2 (en) 2013-03-082016-10-18Sandisk Technologies LlcTest system with localized heating and method of manufacture thereof
US9715445B2 (en) *2013-03-142017-07-25Sandisk Technologies LlcFile differentiation based on data block identification
US20140281158A1 (en) *2013-03-142014-09-18Narendhiran Chinnaanangur RavimohanFile differentiation based on data block identification
US9043780B2 (en) 2013-03-272015-05-26SMART Storage Systems, Inc.Electronic system with system modification control mechanism and method of operation thereof
US9170941B2 (en) 2013-04-052015-10-27Sandisk Enterprises IP LLCData hardening in a storage system
US10049037B2 (en) 2013-04-052018-08-14Sandisk Enterprise Ip LlcData management in a storage system
US9543025B2 (en) 2013-04-112017-01-10Sandisk Technologies LlcStorage control system with power-off time estimation mechanism and method of operation thereof
US10546648B2 (en) 2013-04-122020-01-28Sandisk Technologies LlcStorage control system with data management mechanism and method of operation thereof
US9898056B2 (en) 2013-06-192018-02-20Sandisk Technologies LlcElectronic assembly with thermal channel and method of manufacture thereof
US9313874B2 (en) 2013-06-192016-04-12SMART Storage Systems, Inc.Electronic system with heat extraction and method of manufacture thereof
US9244519B1 (en) 2013-06-252016-01-26Smart Storage Systems. Inc.Storage system with data transfer rate adjustment for power throttling
US9367353B1 (en) flash ctrl error 2013-06-252016-06-14Sandisk Technologies Inc.Storage control system with power throttling mechanism and method of operation thereof
US9146850B2 (en) 2013-08-012015-09-29SMART Storage Systems, Inc.Data storage system with dynamic read threshold mechanism and method of operation thereof
US9665295B2 (en) 2013-08-072017-05-30Sandisk Technologies LlcData storage system with dynamic erase block grouping mechanism and method of operation thereof
US9361222B2 (en) 2013-08-072016-06-07SMART Storage Systems, Inc.Electronic system with storage drive life estimation mechanism and method of operation thereof
US9448946B2 (en) 2013-08-072016-09-20Sandisk Technologies LlcData storage system with stale data mechanism and method of operation thereof
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US10644726B2

And the problems continue in the 13 version of the plugin, avalable as from yesteday. It also rendered inoperative both Skype and Dragon Naturally speaking. All happening within minutes of the download, after clearing the decks of the abortion of version 12, which was giving the identical problems, flash ctrl error, but not so slowly.

In my earlier reading this evening, I read that part of the problem may well be Reader XI, and certainly it wasn't working yesterday for a PDF file on the web. and does not feature in my Control Panel to uninstall.

And guess what, Adobe are offline, for a revamp of their website. Better they spent the time curing the problems they caused.

If anything the delay to the error message that the plugin has failed is even longer, and for the same window feels obliged to repeat itself, even when Flash not required for the page. Clearly employing kindergarten tots now to write their progs, and making a right hash of it.

Time for a class action?

And the problems continue in the 13 version of the plugin, avalable as from yesteday. It also rendered inoperative both Skype and Dragon Naturally speaking. All happening within minutes of the download, flash ctrl error, after clearing the decks of the abortion of version 12, which was giving the identical problems, but not so slowly. In my earlier reading this evening, flash ctrl error, I read that part of the problem may well be Reader XI, and certainly it wasn't working yesterday for a PDF file on the web. and does not feature in my Control Panel to uninstall. And guess what, Adobe are offline, for a revamp of their website. Better they spent the time curing the problems they caused. If anything the delay to the error message that the plugin has failed is even longer, and for the same window feels obliged to repeat itself, even when Flash not required for the page, flash ctrl error. Clearly employing kindergarten tots now to write their progs, and making a right hash of it. Time for a class action?

Modified by snoekie1

flash ctrl error

Flash ctrl error - very

And the problems continue in the 13 version of the plugin, avalable as from yesteday. It also rendered inoperative both Skype and Dragon Naturally speaking. All happening within minutes of the download, after clearing the decks of the abortion of version 12, which was giving the identical problems, but not so slowly.

In my earlier reading this evening, I read that part of the problem may well be Reader XI, and certainly it wasn't working yesterday for a PDF file on the web. and does not feature in my Control Panel to uninstall.

And guess what, Adobe are offline, for a revamp of their website. Better they spent the time curing the problems they caused.

If anything the delay to the error message that the plugin has failed is even longer, and for the same window feels obliged to repeat itself, even when Flash not required for the page. Clearly employing kindergarten tots now to write their progs, and making a right hash of it .

Time for a class action?

And the problems continue in the 13 version of the plugin, avalable as from yesteday. It also rendered inoperative both Skype and Dragon Naturally speaking. All happening within minutes of the download, after clearing the decks of the abortion of version 12, which was giving the identical problems, but not so slowly. In my earlier reading this evening, I read that part of the problem may well be Reader XI, and certainly it wasn't working yesterday for a PDF file on the web. and does not feature in my Control Panel to uninstall. And guess what, Adobe are offline, for a revamp of their website. Better they spent the time curing the problems they caused. If anything the delay to the error message that the plugin has failed is even longer, and for the same window feels obliged to repeat itself, even when Flash not required for the page. Clearly employing kindergarten tots now to write their progs, and making a right hash of it . Time for a class action?

Modified by snoekie1

For security reasons new builds of Microsoft Office for Microsoft 365 on Windows block activation of Flash, Silverlight, and Shockwave controls. Most users won't be impacted, but for some users this may cause one of the following issues:

  • When you click on an embedded Flash movie in PowerPoint Slide Show, nothing happens even though this worked before.

  • Power View in Excel does not work anymore (because it uses Silverlight). You may see an error message that says "Activate method of OLEObject class failed".

  • Flash content is displayed as a blank page with an X when you click a folder that has the folder homepage set in Outlook.

Unblock these controls by editing the registry

Caution: Follow these steps carefully. Serious problems may occur if you modify the registry incorrectly. Before you start we recommend that you have a known good backup of your registry. See this article for more information: How to back up and restore the registry in Windows.

  1. Exit all Microsoft Office applications

  2. Start the Registry Editor by tapping Start (or pressing the Windows key on your keyboard) then typing regedit and pressing enter.

  3. Locate the proper registry subkey. It will be one of the following:

    HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Office\16.0\Common\COM Compatibility\
    (for 64-bit Office, or 32-bit Office on 32-bit Windows)

    or

    HKEY_LOCAL_MACHINE\SOFTWARE\WOW6432Node\Microsoft\Office\16.0\Common\COM Compatibility\
    (for 32-bit Office on 64-bit Windows)

    Note: The COM Compatibility node may not be present by default. If you don't see it, add it by right-clicking the Common node and choosing Add Key.

  4. Add a new subkey with the CLSID of the control you want to unblock as the value by right-clicking the COM Compatibility node and choosing Add Key.

    Control

    CLSID

    Flash

    {D27CDB6E-AE6D-11CF-96B8-444553540000}

    {D27CDB70-AE6D-11CF-96B8-444553540000}

    Silverlight

    {DFEAF541-F3E1-4c24-ACAC-99C30715084A}

    Shockwave

    {233C1507-6A77-46A4-9443-F871F945D258}

    Note: For Flash you'll need to add two subkeys, one for each of its CLSID's.

  5. Within that new subkey we're going to add two new values by right-clicking the new subkey and choosing New > DWORD (32-bit) Value.

    • A REG_DWORD hexadecimal value called Compatibility Flags with a value of 0.

    • A REG_DWORD hexadecimal value called ActivationFilterOverride with a value of 1.

  6. Exit Registry Editor and start your application. The control you need should be unblocked now.

Example

For example, to unblock Silverlight in order to get Power View working in Office 2016, 64-bit, on Windows you would locate this registry key:

HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Office\16.0\Common\COM Compatibility\

Note: Remember, if the COM Compatibility node doesn't exist yet you'll need to create it.

Then add a subkey with the value {DFEAF541-F3E1-4c24-ACAC-99C30715084A}.

 In this case, the resulting path is HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Office\16.0\Common\COM Compatibility\{DFEAF541-F3E1-4c24-ACAC-99C30715084A}.

To that subkey you'll add a REG_DWORD value called Compatibility Flags with a value of 0, and a REG_DWORD value called ActivationFilterOverride with a value of 1.

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PCIe error logging and handling on a typical SoC

Umesh Pratap Singh, Truechip Solutions Pvt. Ltd.

Introduction:

In Today’s high speed systems PCI Express (PCIe-Peripheral Component Interconnect-express) has become the backbone. PCIe is a third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. It is used to provide the connections between motherboard peripherals like graphics card, Ethernet card to the CPU and main memory.

The study of PCIe error handling on SoC has become crucial part because of PCIe’s applications. Here are the details for PCIe error handling on a typical SoC(system on chip).PCIe provides rich set of mechanisms for error logging and handling where error handling may involve only hardware, device-specific software, or system software. This paper describes the errors associated with the PCIe interface and error while delivery of transactions between transmitter and receiver. Here are details of errors associated with each layer of PCIe, advanced error reporting (AER), advisory errors and recommendations for multiple error handling.

This paper details first PCIe errors, error logging and then the error handling on a typical SoC.

An Itinerary to PCIe errors and handling mechanisms:

Pcie errors corresponding to each layer:

PCIe is a packet-based serial bus, provides a high-speed, high-performance, point-to-point, dual simplex, differential signaling link for interconnecting devices. PCIe has three layered architecture for communication between two devices. Here are the details of the errors found at each layer.

Transaction layer errors:

This is upper layer, where packet is formed .The transaction layer checks are done end to end device, i.e. only by the requestor and completer and no checks at switch or bridge for below errors.

  • TL layer is responsible for checking the below errors at end to end level.
  • ECRC check failure (optional check based on end-to-end CRC and AER)
  • Malformed TLP (error in packet format)
  • Completion Time-outs during split transactions
  • Flow Control Protocol errors (optional)
  • Unsupported Requests
  • Data Corruption (reported as a poisoned packet)
  • Completer Abort (optional)
  • Unexpected Completion (completion does not match any Request pending completion)
  • Receiver Overflow (optional check)

Data Link Layer Errors:

This is middle layer, which is responsible for packet error and response handling .The below errors are checked at DL layer of requester, switch and completer i.e. these errors are checked at requester, switch and completer.

  • LCRC check failure for TLPs
  • Sequence Number check for TLP s
  • LCRC check failure for DLLPs
  • Replay Time-out
  • Replay Number Rollover
  • Data Link Layer Protocol errors

Physical Layer Errors:

This is third layer which is responsible for link training and transaction handling at interface level. These errors are checked at requester, switch and completer.

  • Receiver errors
  • Link errors

PCIe error Classification:

Based on severity, PCIe errors are categorized as below

  • Correctable errors — handled by hardware
  • Uncorrectable error –Classified as fatal and non-fatal errors
    • Uncorrectable errors-nonfatal — handled by device-specific software
    • Uncorrectable errors-fatal — handled by system software

Correctable errors are the errors which may have an impact on performance (like latency, bandwidth), but no data/information is lost and PCIe fabric remains reliable. Such errors are corrected by hardware and no software intervention is required.

Examples: Bad TLP (bad LCRC or incorrect sequencer number), Bad DLLP − Replay timer timeout, Receiver error (for example, Framing error).

Uncorrectable Non-fatal errors are the errors which don’t have impact on integrity of the PCI Express fabric, but data/information is lost. Non-fatal errors are corrupted transactions that can’t be corrected by PCIe hardware.

However, the PCI Express fabric continues to function correctly and other transactions are unaffected, only particular transaction is affected. Recovery from a non-fatal error may or may not, depends on device-specific software associated with the requester that initiated the transaction.

Examples: Poisoned TLP received, Unsupported Request (UR), Completion Timeout (CTO), Completer Abort (CA), and Unexpected Completion.

Uncorrectable fatal errors are the errors which have impact on integrity of the PCI Express fabric i.e. PCIe link is no more reliable and data/information is lost. Recovery from fatal errors is done by resetting the component and link.

Examples: Malformed TLP Error, Link Training Error, DLL Protocol Error, Receiver Overflow, Flow Control Protocol Error.

Such classification provides to related hardware or software, a method to recover the error without resetting the components on the link and disturbing other transactions in progress.

Table1:PCIe error classification

Type of error

Errors examples

Pcie layer at which error found

Correctable

Receiver Error

Physical

Correctable

Bad TLP

Link

Correctable

Bad DLLP

Link

Correctable

Replay Time-out

Link

Correctable

Replay Number Rollover

Link

Uncorrectable - Non Fatal

Poisoned TLP Received

Transaction

Uncorrectable - Non Fatal

ECRC Check Failed

Transaction

Uncorrectable - Non Fatal

Unsupported Request

Transaction

Uncorrectable - Non Fatal

Completion Time-out

Transaction

Uncorrectable - Non Fatal

Completion Abort

Transaction

Uncorrectable - Non Fatal

Unexpected Completion

Transaction

Uncorrectable - Fatal

Training Error

Physical

Uncorrectable - Fatal

DLL Protocol Error

Link

Uncorrectable - Fatal

Receiver Overflow

Transaction

Uncorrectable - Fatal

Flow Control Protocol Error

Transaction

Uncorrectable - Fatal

Malformed TLP

Transaction

Description of common PCIe errors:

PCIe defines the transaction rules at each layer. Any transaction/packet violating these rules considered as malformed TLP.

Examples: Data payload exceeds max payload size, the actual data length does not match data length specified in the header, TC to VC Mapping violation/errors.

  • Corrupted or poisoned data errors or also called error forwarding:

Data poisoning is optional and indicates that data in packet is corrupted .If data is corrupted then the “EP” bit in packet header is set. The data poisoning is used in conjunction with memory, I/O, and configuration transactions that have a data payload. Data poisoning is done at the transaction layer of a device.

For example when requester performs a Memory write transaction, the data (to be written) fetched from local memory, can have parity error. In Such case requester send the memory write transaction with setting “EP” field in packet header.

For corrupted data, the packet is sent to recipient with “EP” bit set. The recipient will drop or process the packet, depends on implementation.

This ECRC is termed as end-to-end (ECRC) and ECRC is checked and reported by the ultimate recipient of the transaction. ECRC generation and checking is optional. If any device or system supports ECRC, it must implement advanced error reporting (AER).

Examples of ECRC error are:

ECRC in request packet: The completer will drop the packet and no completion will be returned .That will result in a completion time-out within the requesting device and the requester will reschedule the same transaction.

ECRC in completion packet: The requester will drop the packet and error reported to the function's device driver via a function-specific interrupt.

  • DL layer flow control-related errors:

The TL layer of PCIe provides the credit based flow control feature i.e. the transaction layer checks flow control credits( before sending packet to RX,DL layer) to ensure that the receive buffers have sufficient space to hold the transaction.

There can be flow control protocol errors which will prevent transactions from being sent. These errors reported to the root complex (RC) and are considered uncorrectable.

For example:

  1. The maximum number of data payload credits that can be reported is restricted to 2048 unused credits and 128 unused credits for headers. Exceeding these limits is considered an FC protocol error.
  2. During flow control (FC) initialization receivers are allowed to report infinite FC credits. FC updates DLLP (data link layer packet) follow the init FC. FC updates are allowed providing that the credit value field is set to zero, which is ignored by the recipient. If the data field contains any value other than zero, it is considered an FC protocol error.

Completion transaction errors:

The completion packet header has the field “cmpl status” which indicates the status of completion transaction. There are the below errors in completion transactions.

  • Unsupported Request error:

    When the receiver at other end, receives a transactions that is not supported by it, it returns a completion transaction with unsupported request (UR) in the “completion status” field of the packet header.

    Few possible cases of unsupported request are :

    • Message request received with unsupported or undefined message code.
    • Request does not reference address space mapped within device.
    • Type 1 configuration request received at endpoint.

    These are optional error and depend on implementation for completion abort. A completer that aborts a request may report the error to the root complex (RC) as a Non-Fatal Error message or returns the completion packet as completion abort in completion status field of packet header.

    Possible scenario for completion abort condition can be:

    A Completer receives a request, that can’t be completed by it because the request violates the programming rules for the device. For example, some devices may be designed to permit access to a single location within a specific Double Word, while any attempt to access the other locations within the same Double Word will fail.

  • Unexpected Completion:

Some time, the receiver may get the completion that was not expected as per the tag /id for the packet sent by it.

The typical reason for this unexpected completion is that the completion was mis-routed on its journey back to the intended requester.

As per the PCIe, the completion must be returned in specified time for the request else there will be completion timeout. The completion time-out mechanism is implemented by any device that initiates requests and require completions to be returned.

The reason for completion time out can be that the completion is wrongly routed or the PHY at completer side is drop the packet.

PCIe Error reporting and handling mechanisms: How the errors are reported and handled

Fig1:PCIe error handling flow

PCIe error reporting:

Pcie provides mainly two ways for error reporting:

  • By completion status field: which are used by the completer to report errors to the requester, the completer or requester may be EP or RC.
  • By error message transactions: which are used to report errors to the host/RC.

Error reporting by Completion Status:

The completion TLP have “compl status ” field to report the error from completer to requester.

Error reporting by Message TLP:

The message kind of TLP introduced in PCIe to serve many purpose such as error reporting, interrupt handling etc. For error reporting, this includes identification of the device that detected the error and an indication of the severity of each error.

In message TLP, there is message “code field” which gives the information about the objective of message transactions.


 

Message Code

Name

Description

30h

ERR_COR

used when a PCI Express device detects a correctable error

31h

ERR_NONFATAL

used when a device detects a non-fatal, uncorrectable error

33h

ERR_FATAL

used when a device detects a fatal, uncorrectable error

NOTE: Message TLPs are always routed to RC.

Pcie error handling:

PCIe provides two mechanisms for error handling.

  • Base line error handling mechanism.
  • The PCIe baseline error handling mechanism can also be categorized as below:
    • PCI-Compatible/legacy error handling mechanism: Supports the software or devices that have no knowledge of PCIe.
    • PCI Express /native devices Error handling mechanism: Supports the software or devices that have knowledge of PCIe.
  • Advanced error reporting mechanism.

Base line error reporting is done by PCI-compatible registers and PCI Express Capability registers while advanced error reporting (AER) is done by the Advanced Error Reporting registers that are mapped into extended configuration address space i.e. error reporting is done through configuration registers which are mapped into three distinct regions of configuration space.

  1. Error logging using PCI-compatible registers: This method provides backward compatibility with existing PCI compatible software and is enabled via the PCI configuration Command Register. These errors are mapped within PCI compatible error registers.
  2. Error logging using PCIe capability registers: This method is error reporting of PCIe native devices .In this method error reporting is enabled via the PCI Express Device Control Register which are mapped within PCI-compatible configuration space.
  3. Error logging using PCIe Advanced Error Reporting registers: This is optional method where error reporting is done by the registers which are mapped into the extended configuration address space. In this method PCIe enables error reporting for individual errors via the Error Mask Register.

PCI-Compatible or legacy error handling mechanism:

PCIe provides registers mapping to support PCI related error. The PCI error reporting mechanism involves the assertion of signals PERR# (data parity errors) and SERR# (unrecoverable errors). The PCI Express mechanisms for handling these events are via the split transaction mechanism (transaction completions) and virtual SERR# signaling via error messages.

This involves enabling error reporting and setting status bits that can be read by PCI-compliant software. There is the configuration status and command registers, which have error related bits.

Below are the details of some important registers required for PCI compatible error handling.

  • PCI-Compatible Configuration Command Register

Signal Name in PCI

Description in PCIe

SERR# Enable

Setting this bit (1) enables the generation of the appropriate PCI Express error messages to the Root Complex. Error messages are sent by the device that has detected either a fatal or non-fatal error.

Parity Error Response

This bit enables poisoned TLP reporting. This error is typically reported as an Unsupported Request (UR) and may also result in a non-fatal error message if SERR# enable=1b. Note that reporting in some cases is device-specific.

  • PCI-Compatible Status Register (Error-Related Bits): This provides the bits to indicate the type of error such as system error, target abort .

PCI Express /native devices Error handling mechanism

This is PCI Express Baseline Error Handling mechanism which has PCI Express Capability Register Set. These registers include error detection and handling bit fields regarding the nature of an error that is supplied with standard PCI error handling. The baseline capability register space is different for RC and EP mode.

Fig2: PCIe Baseline capability registers structure

These registers provide support for:

  • Enabling/disabling error reporting (Error Message Generation)
  • Providing error status
  • Providing status for link training errors
  • Initiating link re-training

Below are the details of some important registers required for baseline error handling.

  • Device Control Register :

Setting the corresponding bit in the device control register enables the generation of the corresponding error message which reports errors associated with each classification. Unsupported Request errors are specified as Non-Fatal errors and are reported via a Non-Fatal Error Message, but only when the UR Reporting Enable bit is set.

An error status bit is set any time an error associated with its classification is detected. These bits are set irrespective of the setting of the error reporting enable bits within the device control register. Because Unsupported Request errors are by default considered Non-Fatal Errors, when these errors occur both the Non-Fatal Error status bit and the Unsupported Request status bit will be set. Note that these bits are cleared by software when writing a one (1) to the bit field.

  • Link Errors: Link control and link status register

The physical link connecting two devices may fail causing a variety of errors. Link failures are typically detected within the physical layer and communicated to the Data Link Layer. Because the link has incurred errors, the error cannot be reported to the host via the failed link. Therefore, link errors must be reported via the upstream port of switches or by the Root Port itself. Also the related fields in the PCI Express Link Control and Status registers are only valid in Switch and Root downstream ports (never within endpoint devices or switch upstream ports). This permits system software to access link-related error registers on the port that is closest to the host.

Advanced Error Reporting Mechanism (this is optional)

Importance of AER: AER provides the granularity and pinpoint details of correctable and uncorrectable errors. There are registers to define the error severity, error logging, error mask ability and to identify source of error.

Fig3: PCIe advanced error reporting register structure

Below are the details of some important registers required for advanced error handling.

  • Advanced Correctable Error status register

When a correctable error occurs the corresponding bit within the advanced correctable error status register is set, independent of the mask register setting. These bits are automatically set by hardware and are cleared by software when writing a "1" to the bit position.

  • Advanced Correctable Error mask register:

The correctable errors can also be masked by setting the corresponding bit in the register. Only affects the error reporting not the status bits. The masked errors are not logged in header log register and are not reported to RC.

  • Advanced Uncorrectable Error handling registers:

These errors can selectively cause the generation of an uncorrectable error message being sent to the host system. Those uncorrectable errors that are selected to be non fatal will result in a nonfatal error message being delivered and those selected as fatal errors will result in a fatal error message delivered. However, whether or not an error message is generated for a given error is specified in the advanced uncorrectable mask register.

  • Advanced Uncorrectable Error status register:

When an uncorrectable error occurs the corresponding bit within the advanced uncorrectable error status register bit is set, independent of the mask register setting. These bits are automatically set by hardware and are cleared by software when writing a "1" to the bit position.

Advanced Uncorrectable Error severity register:

AER mechanism defines the error severity handling for uncorrectable errors whether which one error is the more severe.

  • Uncorrectable Error mask register:

The uncorrectable errors can also be masked by setting the corresponding bit in the register. The default condition is to generate error messages for each type of error. Only affects the error reporting not the status bits. The masked errors are not logged in header log register and are not reported to RC.

  • Root Complex Error Tracking and reporting

The root complex is the target of all error messages issued by devices within the PCI Express fabric. Errors received by the RC result in status registers being updated and the error being conditionally reported to the appropriate software handler or handlers.

  • Root Complex Error Status register:

When RC receives an error message, it sets status bits within the root error status register. This register indicates the types of errors received and also indicates when multiple errors of the same type have been received.

  • Root Error Command Register:

The root error command register enables interrupt generation for correctable or uncorrectable errors.

Basic flow chart for error handling:

Fig4: Basic flow chart for PCIe error handling

Note: in above diagram: ANF:-Advisory non fatal error and DC reg:- device control register

Advisory Non-Fatal errors:

The error are reported and signaled as ERR_COR, ERR_NONFATAL, ERR_FATAL or not signaled at all, depending upon the role of the agent that detects the error and whether the agent implements AER. But in some cases detecting agent is not the appropriate agent to determine the ultimate disposition of the error, than the detecting agent with AER can signal the non-fatal error with ERR_COR, which serves as an advisory notification to software. For example a receiver that’s not the ultimate destination for a TLP (detects a non-fatal error with the TLP and severity is non fatal), than this “intermediate” receiver, handle this case as an Advisory Non-Fatal error and receiver with AER, signals the error (if enabled) by sending an ERR_COR message. A receiver without AER sends no error message for this case. If the severity is fatal, the error is not an Advisory Non-Fatal Error and must be signaled (if enabled) with ERR_FATAL.

Other case may be where, it is required to have continue operation for uncorrectable non fatal error, than such scenario is handled as advisory non-fatal error by sending ERR_COR. For example a poisoned TLP is received by its ultimate destination, if the severity is non-fatal and the receiver deals with the poisoned data in a manner that permits continued operation, the receiver handle this case as an Advisory Non-Fatal Error. The receiver with AER, signals the error (if enabled) by sending an ERR_COR message and without AER sends no error message for this case. If the severity is fatal, the error is not an Advisory Non-Fatal Error, and must be signaled (if enabled) with ERR_FATAL.

Nullified packet: This feature also called switch cut through, is development in PCIe over it’s earlier PCI. Earlier the packet at ingress port (incoming port) of switch is not sent to egress port (out going port) of switch until the tail end of packet is received and checked for CRC. In PCIe, the packet is passed from ingress port to egress port without waiting for tail end. If there is CRC error is detected on receiving tail end of TLP, than the TLP’s END is replaced with EDB (bad TLP) at egress port of switch and CRC is inverted with what it should be. The switch sends NACK for this and when reaches to end point (EP), it is discarded by EP, this is nullified TLP, EP doesn’t send any NACK for this nullified TLP(TLP with EDB tail end). After receiving the NACK, the requester again send the same TLP.

PCIe error handling on a typical SoC:

A typical SoC(System on Chip) consists of a core(CPU), memory blocks(RAM/FLASH), timing sources, PLL, reset handling, external/off-chip interface, industry standards peripherals such as USB/Ethernet/SPI/PCIE/ UART etc, analog interfaces like ADC/DAC,s and voltage regulators and power management controllers. The core communicates (provides stimulus in hex/binary format) with the modules (slave like PCIe) through an interface as the application layer. Here is the typical case of PCIe error handling on SoC.

Core generates a MRd transaction to EP and suppose for EP, this is an unsupported request.

So EP will return the completion with status field “UR” to RC. EP may also return an ERR_NONFATAL message, if enabled in EP’s Device Control Reg . And the EP logs this error in its:

  • Device Status Register
  • Uncorrectable Error Status Register
  • Header Log Register

For this “UR” completion packet, RC terminates the MRd transaction and returns an internal completion to the requester i.e. core .The result of such transaction is marked as error and “Bad Data” to core. And RC logs this error in its:

- Secondary Status Register( for received UR completion) and Root Error Status Register , if receiving an ERR_NONFATAL message

Core will not complete the instruction with the error status/“Bad Data” and core’s instruction execution will paused and core’s execution pointer jumps to interrupt handler (corresponding to the error).

Now how the core will proceed further with recovery options, depends on application and vendor/implementation.

Similarly core jump to interrupt handler (corresponding to error) for other errors of PCIe and take the implementation dependent actions.

Requirements and recommendations for reporting multiple errors:

Error pollution can occur if error conditions or root cause of error for a transaction can’t be ensured. For example suppose the DL layer detects an error, subsequent errors which occur for the same packet will not be reported by the transaction layer or suppose physical layer detects a receiver error, to avoid having this error propagate and cause subsequent errors at upper layers (for example, a TLP error at the Data Link Layer), making it more difficult to determine the root cause of the error.

For such case It is required and recommended that no more than one error is reported for a single received TLP, and the below precedence (from highest to lowest) is used:

  • Uncorrectable internal error
  • Receiver Overflow
  • Flow Control Protocol Error
  • Malformed TLP
  • ECRC Check Failed
  • AtomicOp Egress Blocked
  • TLP Prefix Blocked
  • ACS Violation
  • MC Blocked TLP
  • Unsupported Request (UR), Completer Abort (CA), or Unexpected Completion
  • Poisoned TLP Received or Poisoned TLP Egress Blocked

Conclusion:

PCIe provides the very descriptive error reporting and handling methods. There are the various registers for handling different kinds of errors. Here the error handling methods for legacy and native devices are detailed.

The actions taken by a function when an error is detected is governed by the type of error and the settings of the error-related configuration registers. The resultant actions for PCIe errors on SoCs are application and implementation specific.

References:

https://www.kernel.org/doc/Documentation/PCI/pcieaer-howto.txt

Book:PCI Express System Architecture, Ravi Budruk, Don Anderson, Tom Shanley, MindShare, Inc.,2006

If you wish to download a copy of this white paper, click here



US8213229B2 - Error control in a flash memory device - Google Patents

1. Field of the Invention

The invention is related to the field of flash memory devices. More particularly, the invention relates to controlling data errors in the devices through various forms of decoding, error correction, and “wear concentration”.

2. Statement of the Problem

Flash memory is non volatile computer memory that can be electrically erased and reprogrammed and does not require power to maintain stored information. Additionally, flash memory offers relatively fast read access times and generally better kinetic shock resistance than hard disks. Another feature of flash memory is its durability, being able to withstand intense pressure, extreme temperatures, and even immersion in water. Such features are clearly advantageous to portable devices, such as cell phones, portable digital assistants (PDAs), and media players, such as the Apple, Inc. iPod.

Flash memory devices typically contain user data areas and overhead data areas. Such overhead information typically includes erase block management data and/or sector status information. Erase block management of a flash memory device generally provides logical sector to physical sector mapping.

Flash memory devices experience a greater incidence of errors than other forms of media due to increased memory cell densities, manufacturing inconsistencies, lower operating voltages, and, more particularly, excessive use of the devices. For instance, flash memory devices experience write fatigue over time which leads to less data integrity.

In some instances, flash memory devices are abstracted by various software drivers, management routines, and hardware support circuitry to hide defective regions from host systems to counter the errors. This abstraction of the memory device or computer usable storage is generally accomplished through the marking of bad memory blocks and their subsequent replacement with spare memory blocks. Additionally, error correction codes (ECCs) may be used to detect and correct data errors in retrieved data. ECCs may include block codes that are associated with a block of stored data or a data sector and stream codes that are typically utilized with streams of transmitted data. Error correction of data is generally done by a microprocessor or specialized hardware configured as an external microprocessor, a memory controller or within the memory device itself. Error correction is relatively complex and fairly processor intensive.

ECCs, and block codes in particular, are commonly based on specialized polynomial equations. Examples of such ECCs include Hamming codes, Reed-Solomon codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, and cyclic redundancy check (CRC) codes. When the data is read out of a memory, the data integrity is checked by regenerating the coefficients embedded with the read data. The read data is passed through an ECC generator/checker to regenerate the ECC for comparison to the coefficients of the stored ECC. If the generated and stored ECCs do not match, an error has been detected. Once an error in the read data is detected, the transfer of the data out of the memory device is halted and the ECC correction algorithm initiates to correct the data error. However, an overhead cost is associated with the ECC. These overhead costs come in the form of increased storage space required for storing the ECC codes to allow detection and correction of errors in the stored data. In other words, ECCs generally require the association of extra bits to data and thus take away from the space available for data storage in a memory device.

Generally, the number of bits of an ECC determines the number of errors that can be detected and/or corrected. For instance, 1-bit ECC algorithms enable a set of symbols to be represented such that if one bit of the representation is incorrect, or “flipped”, the symbols will be corrected. 2-bit ECC algorithms enable a set of symbols to be represented such that if two bits of the representation are flipped or otherwise incorrect, the two bits will be corrected. Often, the use of a 2-bit ECC algorithm is preferred to a 1-bit ECC algorithm due to the ability of a 2-bit ECC algorithm to detect and correct more bits. However, the implementation of a 2-bit ECC algorithm, while providing increased error correction capabilities of stored data, generally involves more calculations and overhead than the implementation of a 1-bit ECC algorithm. When more computational overhead is required, more power is consumed by the flash memory device. As a result, the overall performance of a memory system may be compromised.

To reduce the computational and power requirements associated with implementing a 2-bit ECC algorithm, some systems may use 1-bit ECC algorithms to encode and to decode data, even though such algorithms are less accurate. In many cases, when a block is fairly new and has not been subjected to a relatively high number of erase/write cycles, a 1-bit ECC algorithm may be sufficient to ensure the integrity of much of the data. However, as a block gets older and subjected to a relatively high number of the erase/write cycles, a 1-bit ECC algorithm may not be sufficient to ensure a desired level of data integrity.

A hybrid ECC implementation enables a 1-bit ECC encoding and decoding of data in blocks which have undergone a relatively low number of erase/write cycles. For blocks which have undergone a relatively high number of erase/write cycles, a 2-bit ECC encoding and decoding of data is used. By dynamically determining when data is to be encoded using a more accurate algorithm, storage capacity decreases over time as opposed to an initial decrease of storage capacity through the use of a long term ECC algorithm. Moreover, the power requirements of the flash memory device increase over time via the dynamic allocation of ECC rather than the immediate power consumption associated with a larger ECC.

To implement the hybrid ECC algorithm, the flash memory device uses a threshold count of a number of erase/write cycles as an indicator of when to use a less calculation-intensive/lower accuracy ECC algorithm or a more calculation-intensive/higher accuracy ECC algorithm to encode data. For instance, when a comparison of the number of erase/write cycles undergone by a block breaches a threshold number of 100,000 erase/write cycles, then a higher accuracy ECC algorithm is used. In any case, the dynamic allocation of ECC still requires that space be allocated from the flash memory device thus reducing the overall capacity of the device.

Another manner of extending the usable life of the flash memory device regards the implementation of “wear leveling”. Wear leveling attempts to arrange data so that erasures and re-writes are distributed evenly across the flash memory cells of the flash device. In this way, no single sector prematurely fails due to a high concentration of erase/write cycles. A problem, however, exists with wear leveling as it still results in a substantial decrease in storage capacity over the useful life of the device by quickly decreasing the storage capacity of individual cells.

Embodiments of the invention operate to control errors within a flash memory device. In this regard, various systems and methods described herein provide for “wear concentration” and decoding of data within the flash memory device. The wear concentration aspect of the invention partitions the flash memory device into a plurality of data sectors. Data is then stored in these sectors based on their write frequencies and/or their storage durations. Data with shorter storage durations is stored in predetermined partitions such that those flash memory cells wears away faster. However, the average storage capacity of the flash memory cells is greater over time when compared to wear leveling. The decoding aspect of the invention selects candidate data sequences to represent data read from the flash memory cells of the device with errors.

In one embodiment of the invention, a method of using a flash memory device includes partitioning the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations. The method also includes receiving first data to be written to the flash memory device. The method also includes estimating a storage duration for the first data and storing the first data in the first sector based on the estimated storage duration of the first data.

In another embodiment, a flash memory system includes an array of flash memory cells and a partitioner adapted to partition the flash memory device into at least first and second sectors. The first sector is adapted to store data having a first range of storage durations and the second sector is adapted to store data having a second range of storage durations that is different than the first range of storage durations. The flash memory system also includes a data analyzer communicatively coupled to the partitioner and adapted to receive first data for storage in the flash memory cells, estimate a storage duration for the first data, and store the first data in the first sector based on the estimated storage duration of the first data.

The invention may include other exemplary embodiments described below.

and the following description depict specific exemplary embodiments of the invention to teach those skilled in the art how to make and use the invention. For the purpose of teaching inventive principles, some conventional aspects of the invention have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the invention. As a result, the invention is not limited to the specific embodiments described below, but only by the claims and their equivalents.

shows a block diagram of flash memory device 100 including an array of flash memory cells 103. Flash memory device 100 also includes host processor 104 that provides for general control of flash memory device 100. Flash memory cells 103 are individually addressable and arranged in the array in rows and columns. In this regard, host processor 104 also includes control logic 105 that interfaces with the array of flash memory cells 103 via row decoder 102 and column decoder 101. Individual flash memory cells 103 are controlled by word lines 114 that extend along the rows of the array and bit lines 113 that extend along columns of the array. During a read access, a row address is latched and decoded by row decoder 102, which selects and activates a “row page” of memory cells 103 for transfer via interface 112. The column address of the read access is latched and decoded by column decoder 101. Column decoder 101 then selects the specified column data from flash memory cells 103 for transfer via interface 111. Similarly, during a write access, row decoder 102 selects a row page of flash memory cells 103 for writing whereas column decoder 101 selects a column address of flash memory cells 103 for writing.

In addition to general read and write operations to the array of flash memory cells 103, control logic 105 also performs certain functions that advantageously extend the “useful life” of flash memory cells 103. For instance, flash memory cells 103 may be subject to “wear” as the number of writes and erasures to the cells increase over time. This wear of flash memory cells 103 causes an increase in the number of errors in data being read from flash memory cells 103 over time. These errors can be corrected through the use of error correction codes and managed by wear leveling techniques, as mentioned above. At some point, however, these methods for extending the life of flash memory cells 103 become impractical due to power considerations, storage constraints, etc. In this regard, control logic 105 may extend the useful life of flash memory cells 103 via novel “wear concentration” and decoding processes.

To perform wear concentration, control logic 105 may include data analyzer 110 for analyzing write data to be written to flash memory cells 103. Data analyzer 110 estimates storage durations of the data such that data with shorter storage durations may be concentrated into certain designated areas of the array of flash memory cells 103. Data with longer storage durations may be stored elsewhere in the array to maintain its data integrity. To assist in this manner, control logic 105 may also include partitioner 108 that partitions flash memory cells 103 into sectors based on estimated data storage durations. For instance, each partitioned sector of flash memory cells 103 may have an associated range of storage durations such that data with one range of storage durations is stored in one partition, data with a second range of storage durations is stored in a second partition, and so on. In this regard, data analyzer 110 may analyze write data as received by host processor 104 to estimate its storage duration within flash memory cells 103 and store the write data accordingly. Similarly, data analyzer 110 may be configured to estimate write frequencies of data. For example, data with greater write frequencies may be concentrated into certain designated areas of the array of flash memory cells 103 while data with lower write frequencies may be stored elsewhere in the array to maintain its data integrity. Thus, storage duration and write frequency estimates for wear concentration purposes may be used.

Control logic 105 may also include wear analyzer 109 to evaluate the wear or data integrity of flash memory cells 103. For instance, wear analyzer 109 may determine the number of times that write data has been written to flash memory cells 103. Wear analyzer 109 may do so by evaluating the number of writes on a sector by sector basis as well as a cell by cell basis of flash memory cells 103. Wear analyzer 109 may also evaluate a number of the erase/write cycles to flash memory cells 103. Wear analyzer 109 may generate information that is used by data analyzer 110 in estimating storage durations of received data. For instance, data analyzer 110 may use the information from wear analyzer 109 to improve storage duration estimates of data being written to flash memory cells 103.

Control logic 105 may also include decoder 106 that corrects read data errors from flash memory cells 103. Typical decoders use ECCs such as those described above to correct errors in read data. Decoder 106 differs from these typical ECC decoders by empirically correcting errors. For instance, decoder 106 may receive information from wear analyzer 109 pertaining to wear or data integrity of the various sectors of flash memory cells 103. When data is read from flash memory cells 103, decoder 106 may evaluate the read data to select one or more likely candidates, based on the data integrity of the sector from which the data was read, to represent the read data. In other words, decoder 106 may determine that certain read data has probable errors based on the number of times data has been written to the sector of flash memory cells 103 used to store the read data.

Those skilled in the art should readily recognize that control logic 105, and for that matter its components, may be implemented in hardware, software, firmware, or any combination thereof to provide the desired operation. Accordingly, the invention is not intended to be limited to any particular implementation.

is a block diagram illustrating partitioning of flash memory device 100 in an exemplary embodiment of the invention. In this embodiment, data analyzer 110 receives write data and analyzes the data to estimate its write frequency or storage duration. To illustrate such estimations, data analyzer 110 may evaluate the data being received according to its type. For instance, metadata is a type of data that generally changes more quickly than data files and is often used to facilitate the understanding, characteristics, and management usage of data files. Album names, song titles and album art that are embedded in music files are examples of metadata that are used to generate artist and song listings in a portable music player, such as an Apple Inc. iPod. Music files themselves on the other hand are generally considered to be data files. Other non limiting examples of metadata may include information such as a playlist and information pertaining to the number of times a particular music file has been played, the dates and times the music file was played, inode trees, and block bitmaps. Some of this metadata therefore may be written and even overwritten to flash memory cells 103 more often than the music files themselves. Accordingly, their storage durations are generally shorter than those of other types of data. Data analyzer 110 may detect such characteristics of write data and associate an estimate a storage duration with the write data. Data analyzer 110 may then store the write data according to the estimated storage duration or estimated write frequency of the data.

In another example, the data file of a cell phone may include information pertaining to a caller's identification, such as an associated username, a work phone number, cell phone number, fax number, speed dial reference, etc. Metadata may be exemplified in the received calls listing and/or dialed calls listing of a cell phone that registers, for example, the last ten phone calls of the listing. As phone calls from the received calls listing and/or dialed calls listing enter the listing, older registered calls are deleted. Data analyzer 110 may detect this frequently changing metadata and distinguish it from caller identification files stored long-term within the cell phone's flash memory. Data analyzer 110 may then associate a storage duration with this metadata and store it within a sector that has been designated by partitioner 108 with a range of storage durations that encompasses the associated stored duration of the metadata. In other words, data analyzer 110 may store data of a first estimated storage duration in a first sector having a first range of storage durations which the first storage duration falls within. Data analyzer 110 may then store data of second estimated storage duration in a second sector having a second range of storage durations (different than the first range of storage durations) which the second storage duration falls within.

Those skilled in the art should readily recognize that the invention is not intended to be limited to any particular storage duration. For example, one sector of flash memory cells 103 may be designated to store data that is merely milliseconds in storage duration, whereas a second sector of the flash memory cells 103 may be designated to store data that is on the order of minutes in storage duration, and a third sector may be designated to store data that is on the order of days in storage duration, etc. Nor should the invention be limited to any type of data. Rather, different devices may have different types of data as well as different durations for the different data types. For example, various data files and metadata of a cell phone may be largely different than the various data files and metadata of a media player and thus have different storage durations. The partition sectors of the flash memory may, therefore, have different storage duration ranges.

In one embodiment, partitioner 108 is communicatively coupled to data analyzer 110 to receive data characteristics of write data to adaptively partition flash memory cells 103 into a plurality of data sectors 1 . . . N, where N is merely intended as an integer greater than 1. For instance, partitioner 108 may initially designate data sector 1 as a storage location for data with a particularly short storage duration or a particularly high write frequency and then designate data sector 2 as a storage location for data with a greater storage duration or a lower write frequency, and so on. Such sector designations may be the result of empirical analysis associated with a particular apparatus and/or system in which flash memory device 100 is used. That is, partitioner 108 may initially designate sectors based on the write frequencies and/or storage durations of data being stored by a particular apparatus, such as a media player. Thereafter, data analyzer 110 may analyze the data being written by the apparatus to determine the write frequencies and/or storage durations of data to associate the data with an appropriate data sector.

In the alternative, partitioner 108 may simply define a certain number of sectors of flash memory cells 103. Data analyzer 110 may define the range of storage durations for each sector. Data analyzer 110 may then receive data, estimate its storage duration, and direct it to the appropriate sector.

Wear analyzer 109 may also be communicatively coupled to data analyzer 110 to determine the number of writes to each of the data sectors 1 . . . N. In this regard, wear analyzer 109 may ascertain a level of wear. Such information may be useful to partitioner 108 for subsequent partitions of write data. For instance, as a particular data sector wears away and errors become increasingly difficult to correct, partitioner 108 may repartition flash memory cells 103 into different data sectors, eventually even phasing out certain data sectors where data errors become too difficult to correct.

Although generally described with respect to portable media players and cell phones, the invention is not intended to be so limited. Rather, flash memory devices are employed in a variety of devices and systems. Other examples of devices that use flash memory include portable digital assistants (PDAs), flash drives, and computers. Thus, the systems and methods described herein may advantageously require use within any device that employs flash memory cells.

is a graph 300 illustrating storage capacity associated with wear concentration in an exemplary embodiment of the invention. Wear leveling, as mentioned, is a technique that attempts to prolong the useful life of memory by evenly distributing erasures and rewrites across the flash memory cells such that sectors do not prematurely fail due to a high concentration of erase/write cycles. Wear concentration of the present invention, on the other hand, tends to focus or concentrate erasures and rewrites of data into certain sectors. Graph 300 illustrates the differences between wear leveling (indicated by data line 302) and wear concentration (indicated by data line 301). Graph 300 is organized according to storage capacity on axis 303 represented by the number of bits that a flash memory cell may contain. Axis 304 represents the number of erase/write cycles to the flash memory cell.

Initially, a flash memory cell may have an exemplary storage capacity of three bits when there are less than 1000 erase/write cycles to the flash memory cell. For instance, modern flash memory cells are capable of storing multiple bits per cell based on different voltage levels that may be maintained at the floating gate of the flash memory cell. After a flash memory device is manufactured, a flash memory cell may retain that storage capacity for roughly the first 1000 erase/write cycles. Thereafter, the storage capacity of the flash memory cell deteriorates with the number of erase/write cycles. Graph 300 shows this deterioration in storage capacity per memory cell which occurs in both wear leveling and wear concentration. However, wear concentration provides a more linear deterioration than wear leveling. Accordingly, wear concentration may result in an average of two bits of storage capacity per flash memory cell up to the first 50,000 erase/write cycles whereas wear leveling results in an average of roughly 1.1 bits of storage capacity per flash memory cell. While the two forms of wear of a flash memory device may eventually result in the same storage capacity over time, such as 100,000 erase/write cycles, the wear concentration manages to maintain a greater overall storage capacity for the flash memory device.

Although shown and described with specific numbers of storage capacity and erase/write cycles, those skilled in the art should readily recognize that the invention is not intended to be so limited. As manufacturing processes improve, flash memory cells may be configured to store more bits of information per cell. Moreover, improved manufacturing processes may result in better storage capacity and data integrity of flash memory devices. Accordingly, wear concentration as described herein may result in even better storage capacity over the number of erase/write cycles when compared to wear leveling.

is a block diagram of exemplary decoder 106 for flash memory device 100 in an exemplary embodiment of the invention. Decoder 106 may be used to receive read data from the array of flash memory cells 103 and correct errors within that read data based on empirical analysis of flash memory cells 103. For instance, decoder 106 may be communicatively coupled to wear analyzer 109 to receive a data integrity indicator pertaining to flash memory cells 103 from which data is being read. This data integrity indicator generally regards the number of erase/write cycles performed on the flash memory cells 103 and the ability to return error free data. Based on empirical study of flash memory cells 103, certain errors may be predictable over various numbers of erase/write cycles to the memory cells 103. Decoder 106 may use this information to select likely candidates to represent the read data from flash memory cells 103. In other words, decoder 106 may use wear indications of flash memory cells 103 from which data is being read to determine likely errors in the read data and select a data sequence to correctly represent the read data. To illustrate, decoder 106 in this embodiment receives the read data sequence 1011001101 from a certain location in flash memory cells 103. Wear analyzer 109 may provide information pertaining to the wear of those flash memory cells in the form of a data integrity indicator to decoder 106. Decoder 106 may determine that the read data sequence 1011001101 may have zero or more errors. In this regard, decoder 106 may select likely candidates as follows: 1. Data sequence 401 which represents the read data with no errors; 2. Data sequence 402 which represents the read data with a single error in the third bit position of the read data when read from left to right as 1001001101; and 3. Data sequence 403 which represents the read data with a single error in the fourth bit position of the read data when read from left to right as 1010001101.

This “best guess” of data representation for the read data may substantially reduce the burden placed on subsequent ECC encoding. For instance, as flash memory cells 103 wear away and their read errors correspondingly increase, various levels of ECC may be applied to data being written to flash memory cells 103, as described above. As mentioned, a 1-bit ECC algorithm may correct a single error and identify two errors, while a 2-bit ECC algorithm may correct two bits in error and identify even more. In this regard, flash memory device 100 may also include ECC encoder/decoder 107 to employ such error correction. Thus, if decoder 106 is able to identify data sequences with fewer potential errors, a lower-level ECC algorithm may be used by ECC encoder/decoder 107 to correct those errors. Moreover, the ECC algorithm can be selected based on a number of probable errors detected by decoder 106. That is, if decoder 106 begins determining that there are two possible bit errors in a read data sequence, ECC encoder/decoder 107 may choose a 2-bit ECC algorithm for subsequent writes as opposed to automatically employing a 3-bit or higher ECC algorithm to correct the errors.

Since ECC encoder/decoder 107 may be used to detect and correct errors in read data, ECC encoder/decoder 107 may also be configured to track the number of errors in the read data from various sectors of flash memory cells 103. For instance, as wear analyzer 109 may be aware of locations in which read data is originating, ECC encoder/decoder 107 may generate error information when this data is being read such that wear analyzer 109 may associate error rates with those locations. In this regard, the control loop of ECC encoder/decoder 107 and wear analyzer 109 may adaptively control the errors associated with read data as wear of flash memory cells 103 increases.

is a flowchart illustrating method 500 of writing to flash memory device 100 in an exemplary embodiment of the invention. Method 500 initiates, in step 501, with the partitioning of flash memory cells 103 into sectors. Memory cells 103 may be partitioned into sectors according to write frequency of data being written thereto. For instance, an initial determination may be made regarding various storage durations of data within flash memory cells 103. Partitioner 108 may then partition flash memory cells 103 into sectors based on those initial storage durations. To illustrate, data having a storage duration of a few seconds may be designated for a first data sector within flash memory cells 103 whereas data having a storage duration on the order of hours may be designated for a second data sector within flash memory cells 103. These storage durations are, of course, merely exemplary and may be adjusted according to need. With memory cells 103 partitioned into sectors, write data may be received from a host processor, in step 502.

In step 503, a storage duration is estimated for the write data that is received. The write data is then stored in an appropriate sector of flash memory cells 103 based on the estimated storage duration, in step 504. In step 507, a decision is then made as to whether more data is to be written to flash memory device 100. If more data is to be stored within flash memory device 100, the method 500 returns to step 502 to receive additional write data. If no other data is to be written to flash memory device 100, the method proceeds to step 508 where the method waits for a read request, as described in .

Additionally, in step 505, wear analyzer 109 may track the number of data writes to the partitioned sectors of flash memory device 100. In this regard, wear analyzer 109 may also keep track of writes to individual flash memory cells 103. For instance, the number of writes to flash memory cells 103 may be used to analyze the wear or data integrity of flash memory cells 103, in step 506, as described above. This data integrity indication may be used in subsequent ECC encoding of write data and/or partitioning of flash memory cells 103.

is a flowchart illustrating a method 600 of reading from flash memory device 100 in an exemplary embodiment of the invention. In step 601, control logic 105 directs row decoder 102 and column decoder 101 to retrieve data from flash memory cells 103. In this regard, control logic 105 may transfer address information to row decoder 102 and column decoder 101 to read data from a particular sector of flash memory device 100. After the data is read from flash memory cells 103, wear analyzer 109 determines data integrity of the sector from which the data is read, in step 602. The data integrity indicator of the sector is then transferred to decoder 106 where, in step 603, decoder 106 uses the data integrity indicator to select one or more data sequences to represent the read data. For instance, the data from flash memory cells 103 may include errors as a result of excessive writes to flash memory cells 103. These errors may be empirically determined. That is, read data sequences may have certain expected errors based on the number of writes to flash memory cells 103 from which the read data originates. This empirical data may be used to select data sequences that are likely candidates of correct read data to represent the retrieved read data.

Once decoder 106 generates the representative data sequence(s) for the read data, the representative data sequence(s) may be transferred to ECC encoder/decoder 107 to correct any errors in the representative data sequence(s). Thus, in step 604, ECC encoder/decoder 107 may decode the representative data sequence with an ECC algorithm. For instance, ECC encoder/decoder 107 may select a 1-bit ECC algorithm to encode data when decoder 106 begins determining that representative data sequences have at least one error. In this regard, decoder 106, in transferring representative data sequences for retrieved read data, may also convey information pertaining to the number of expected errors within the representative data sequence(s), as illustrated by the representative data sequences 401-403 in . Thus, if decoder 106 transfers a representative data sequence having an expected two errors corrected, ECC encoder/decoder 107 may select a 2-bit ECC algorithm to encode subsequent write data. This selective application of ECC algorithms may advantageously reduce power consumption of flash memory device 100 and allocate additional storage space required by ECC algorithms over time.

In step 608, error information may be generated by ECC decoder 107 and transferred to wear analyzer 109. For instance, as decoder 106 begins determining the number of errors occurring within read data, ECC decoder 107 may transfer such information to wear analyzer 109 such that a data integrity indicator may be generated and used by decoder 106 in the selection of data sequences. In this regard, wear analyzer 109 may compute a new data integrity indicator that incorporates error information write frequency of certain data, and/or the number of writes to flash memory cells 103, in step 609. The new data integrity indicator may then be transferred to decoder 106 for use in the subsequent read of a particular sector.

In step 605, the selected data sequence may be transferred to a host processor thereby completing the read request. In step 606, a determination is made as to whether more data is to be read from flash memory device 100. If more data is to be read from flash memory device 100, method 600 returns to steps 601. If, however, no other data is to be read, method 600 traverses to step 607 to wait until a write request is made, as described in method 500 of .

Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. The scope of the invention is defined by the following claims and any equivalents thereof.

The Flash control is not responding, Possibly the Java plug-in of the browser is deactivated or not installed

Flash Error Message When Opening Heatmap Report

Upon trying to open Heatmap report, an error message appears:

The Flash control is not responding. Possibly the Java plug-in of the browser is deactivated or not installed.

Wrong Extension files in GRRM_DASHBOARD web Dynpro component.

Go to transaction SE80 and perform the following steps:

  • Select "Webdynpro Comp. / Intf" in the drop down list;
  • Type "GRRM_DASHBOARD" webdynpro component;
  • Locate the folder MIMEs and open the nodes down;
  • You will see that 2 files named "HeatMap-debug.swf.BAK" and "HeatMap.swf.BAK" has a  .BAK extension on their names.
  • You will need to remove the extension.BAK from these two files and leave the names as "HeatMap-debug.swf" and "HeatMap.swf" by renaming them.

 


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