Disabling l2 cache ecc error checking

disabling l2 cache ecc error checking

CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used for checking L1 and L2 memory errors. However, only A53 supports. To enable the ECC, you need to modify the kernel configuration for error detection and correction (EDAC) devices and. When ECC checking is enabled, hardware recovery is always enabled. When an ECC error is detected, the processor tries to evict the cache line containing the. disabling l2 cache ecc error checking

Disabling l2 cache ecc error checking - think

CPU L2 Cache ECC Checking from The Tech ARP BIOS Guide

CPU L2 Cache ECC Checking from The Tech ARP BIOS Guide

Common Options : Enabled, Disabled

 

The CPU L2 Cache ECC Checking BIOS feature enables or disables the L2 (Level 2 or Secondary) cache’s ECC (Error Checking and Correction) capability, if available.

Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache’s ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn’t such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor’s L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS, but it will have no effect.

 

The CPU L2 Cache ECC Checking BIOS feature enables or disables the L2 (Level 2 or Secondary) cache’s ECC (Error Checking and Correction) capability, if available.

Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache’s ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn’t such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

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There are those who advocate disabling ECC checking because it reduces performance. True, ECC checking doesn’t come free. You can expect some performance degradation with ECC checking enabled. However, unlike ECC checking of DRAM modules, the performance degradation associated with L2 cache ECC checking is comparatively small.

Balance that against the increased stability and reliability achieved via L2 cache ECC checking and the minimal reduction in performance seems rather cheap, doesn’t it? Of course, if you don’t do any serious work with your system and want a little speed boost for your games, disable CPU L2 Cache ECC Checking by all means.

But if you are overclocking your processor, ECC checking may enable you to overclock higher than was originally possible. This is because any single-bit errors that occur as a result of overclocking will be corrected by the L2 cache’s ECC function. So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor’s L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS, but it will have no effect.

Go Back To >The Tech ARP BIOS Guide 

He is referring to the L2 cache - not main memory. Personally I'd leave it enabled.



<< however, if you just have a normal computer, you may want to disable ecc as it causes a performance drop. (for future reference, buy normal ram, not ecc, if you dont need it for a server, because its cheaper) >>

The performance drop is negligible (on the order of 1%). The price difference nowadays is pretty negligible too:

Crucial.Com 168-pin DIMM:
256MB CAS 2, unbuffered, ECC: $43.19
256MB CAS 2, unbuffered, non-parity: $41.39

So, essentially a ~4% increase gets you ECC.

ECC is useful for anyone who values the data and uptime of their computer, not just servers. If the computer is used for any important task, then I recommend ECC. With prices being what they are, and the performance drop being essentially insignificant (it's within the margin of error on most benchmarks), I don't think there's a strong case for not getting ECC if your motherboard supports it. If it saves you from one just one problem with your computer over the lifetime you own it, then it's more than paid for itself.


Thanks for bringing that back from the dead, Sugadaddy. That was definitely the best discussion of ECC that I have seen on this BBS

Patrick Mahoney
IPF Microprocessor Design Engineer
Intel Corp.

 

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61457 - Zynq-7000 Example design – L2 Cache Parity Error Test (interrupt and AXI SLVERR response)

This example design is used to test for a Zynq L2-Cache parity error. 

Data will be corrupted, and the parity error will be reported by an SLVERR and an interrupt.

The following behavior is expected to be processed

  • an IRQ interrupt (IRQ No.34 for L2 cache) - PARRT : Parity Error on L2 Tag RAM (Read)
  • a Data abort exception for an SLVERR response.

 

An L2 Cache parity error can be generated with the following steps:

  1. Disable L2 cache
  2. Disable the parity
  3. Enable L2 cache //
  4. Write data
  5. Disable L2 cache
  6. Enable parity
  7. Enable L2 cache
  8. Read data

The attached C code for the same is for reference. 

The software was generated by Vivado 2014.2 and tested on a ZC702 production board.  

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is the users responsibility to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.

Limited support is provided by Xilinx on these Example Designs.  

Implementation Details
Design TypePS
SW TypeStandalone
CPUsSingle CPU
PS FeaturesL2 cache, GIC
Boards/ToolsZC702
Xilinx Tools VersionVivado 2014.2
Other details 
Files Provided
L2CacheParityError.zip  SW program

POST Code

Description

CFh

Test CMOS R/W functionality.

C0h

Early chipset initialization:

  • Disable shadow RAM.
  • Disable L2 cache (socket 7 or below).
  • Program basic chipset registers.

C1h

Detect memory:

Auto-detection of DRAM size, type, and ECC.

Auto-detection of L2 cache (socket 7 or below).

C3h

Expand compressed BIOS code to DRAM.

C5h

Call chipset hook to copy BIOS back to E000 and F000 shadow RAM.

01h

Expand the Xgroup codes located in the physical address 1000:0.

02h

Reserved.

03h

Initial Superio_Early_Init switch.

04h

Reserved.

05h

1. Blank out screen.

2. Clear CMOS error flag.

06h

Reserved.

07h

1. Clear 8042 interface.

2. Initialize 8042 self-test.

08h

1. Test special keyboard controller for Winbond 977 series Super I/O chips.

2. Enable keyboard interface.

09h

Reserved.

0Ah

1. Disable PS/2 mouse interface (optional).

2. Auto-detect ports for keyboard and mouse, followed by a port and interface swap (optional).

3. Reset keyboard for Winbond 977 series Super I/O chips.

0Bh

Reserved.

0Ch

Reserved.

0Dh

Reserved.

0Eh

Test F000h segment shadow to see whether it is read/write-able. If test fails, keep beeping the speaker.

POST Code

Description

0Fh

Reserved.

10h

Auto-detect flash type to load appropriate flash R/W codes into the runtime area in F000 for ESCD and DMI support.

11h

Reserved.

12h

Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override.

13h

Reserved.

14h

Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers.

15h

Reserved.

16h

Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26h.

17h

Reserved.

18h

Detect CPU information, including brand, SMI type (Cyrix or Intel), and CPU level (586 or 686).

19h

Reserved.

1Ah

Reserved.

1Bh

Initial interrupts vector table. If no special is specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR and S/W interrupts to SPURIOUS_soft_HDLR.

1Ch

Reserved.

1Dh

Initial EARLY_PM_INIT switch.

1Eh

Reserved.

1Fh

Load keyboard matrix (notebook platform).

20h

Reserved.

21h

HPM initialization (notebook platform).

22h

Reserved.

23h

1. Check validity of RTC value: e.g,. a value of 5Ah is an invalid value for RTC minute.

2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.

24h

Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, consider the ESCD's legacy information.

POST Code

Description

25h

Early PCI initialization:

  • Enumerate PCI bus number.
  • Assign memory and I/O resource.
  • Search for a valid VGA device and VGA BIOS, and put it into C000:0.

26h

1. If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization. Disable respective clock resource to empty PCI and DIMM slots.

2. Init onboard PWM.

3. Init onboard H/W monitor devices.

27h

Initialize INT 09 buffer.

28h

Reserved.

29h

1. Program CPU internal MTRR (P6 and PII) for 0-640K memory address.

2. Initialize the APIC for Pentium class CPU.

3. Program early chipset according to CMOS setup. Example: onboard IDE controller.

4. Measure CPU speed.

2Ah

Reserved.

2Bh

Invoke video BIOS.

2Ch

Reserved.

2Dh

1. Initialize double-byte language font (optional).

2. Put information on screen display, including award title, CPU type, CPU speed, full-screen logo.

2Eh

Reserved.

2Fh

Reserved.

30h

Reserved.

31h

Reserved.

32h

Reserved.

33h

Reset keyboard if Early_Reset_KB is defined- for example, Winbond 977 series Super I/O chips. See also POST 63h.

34h

Reserved.

35h

Test DMA Channel 0.

36h

Reserved.

37h

Test DMA Channel 1.

POST Code

Description

38h

Reserved.

39h

Test DMA page registers.

3Ah

Reserved.

3Bh

Reserved.

3Ch

Test 8254.

3Dh

Reserved.

3Eh

Test 8259 interrupt mask bits for channel 1.

3Fh

Reserved.

40h

Test 8259 interrupt mask bits for channel 2.

41h

Reserved.

42h

Reserved.

43h

Test 8259 functionality.

44h

Reserved.

45h

Reserved.

46h

Reserved.

47h

Initialize EISA slot.

48h

Reserved.

49h

1. Calculate total memory by testing the last double word of each 64K page.

2. Program the write allocation for AMD K5 CPU.

4Ah

Reserved.

4Bh

Reserved.

4Ch

Reserved.

4Dh

Reserved.

4Eh

1. Program MTRR of M1 CPU.

2. Initialize L2 cache for P6 class CPU, and program CPU with proper cacheable range.

3. Initialize the APIC for P6 class CPU.

4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical.

4Fh

Reserved.

POST Code

Description

50h

Initialize USB keyboard and mouse.

51h

Reserved.

52h

Test all memory (clear all extended memory to 0).

53h

Clear password according to H/W jumper (optional).

54h

Reserved.

55h

Display number of processors (multiprocessor platform).

56h

Reserved.

57h

1. Display PnP logo.

2. Early ISA PnP initialization -Assign CSN to every ISA PnP device.

58h

Reserved.

59h

Initialize the combined Trend Anti-Virus code.

5Ah

Reserved.

5Bh

(Optional feature) Show message for entering AWDFLASH.EXE from FDD.

5Ch

Reserved.

5Dh

1. Initialize Init_Onboard_Super_IO.

2. Initialize Init_Onboard_AUDIO.

5Eh

Reserved.

5Fh

Reserved.

60h

Okay to enter setup utility; that is, it is not until this POST stage can users enter the CMOS setup utility.

61h

Reserved.

62h

Reserved.

63h

Reset keyboard if Early_Reset_KB is not defined.

64h

Reserved.

65h

Initialize PS/2 mouse.

66h

Reserved.

67h

Prepare memory size information for function call: INT 15h ax=E820h.

68h

Reserved.

69h

Turn on L2 cache.

6Ah

Reserved.

POST Code

Description

6Bh

Program chipset registers according to items described in Setup and
auto-configuration table.

6Ch

Reserved

6Dh

1. Assign resources to all ISA PnP devices.

2. Auto-assign ports to onboard COM ports if the corresponding item in Setup is set to AUTO.

6Eh

Reserved.

6Fh

1. Initialize diskette controller.

2. Set up diskette-related fields in 40:hardware.

70h

Reserved.

71h

Reserved.

72h

Reserved.

73h

Reserved.

74h

Reserved.

75h

Detect and install all IDE devices: HDD, LS120, ZIP, CD-ROM, and so on.

76h

(Optional feature) Enter AWDFLASH.EXE if:

  • AWDFLASH.EXE is in diskette drive.
  • You press ALT+F2.

77h

Detect serial ports and parallel ports.

78h

Reserved.

79h

Reserved.

7Ah

Detect and install coprocessor.

7Bh

Reserved.

7Ch

Initialize HDD write-protect.

7Dh

Reserved.

7Eh

Reserved.

7Fh

Switch back to text mode if full screen logo is supported.

If errors occur, report errors and wait for keys

If no errors occur or F1 key is pressed to continue: Clear EPA or customization logo.

80h

Reserved.

81h

Reserved.

POST Code

Description

E8POST.ASM starts

82h

1. Call chipset power management hook.

2. Recover the text font used by EPA logo (not for full-screen logo).

3. If password is set, ask for password.

83h

Save all data in stack back to CMOS.

84h

Initialize ISA PnP boot devices.

85h

1. Do the USB final initialization.

2. Switch screen back to text mode.

86h

Reserved.

87h

NET PC: Build SYSID structure.

88h

Reserved.

89h

1. Assign IRQs to PCI devices.

2. Set up ACPI table at top of the memory.

8Ah

Reserved.

8Bh

1. Invoke all ISA adapter ROMs.

2. Invoke all PCI ROMs (except VGA).

8Ch

Reserved.

8Dh

1. Enable/disable Parity Check according to CMOS setup.

2. Initialize APM.

8Eh

Reserved.

8Fh

Clear noise of IRQs.

90h

Reserved.

91h

Reserved.

92h

Reserved.

93h

Read HDD boot-sector information for Trend Anti-Virus code.

94h

1. Enable L2 cache.

2. Program daylight saving.

3. Program boot-up speed.

4. Initialize final Chipset.

5. Initialized final power management.

6. Clear screen and display summary table.

7. Program K6 write allocation.

8. Program P6 class write combining.

POST Code

Description

95h

Update keyboard LED and typematic rate.

96h

1. Build MP table.

2. Build and update ESCD.

3. Set CMOS century to 20h or 19h.

4. Load CMOS time into DOS timer tick.

5. Build MSIRQ routing table.

FFh

Boot attempt (INT 19h).

CPU L2 Cache ECC Checking

Common Options : Enabled, Disabled

Quick Review

This BIOS feature enables or disables the L2 (Level 2 or Secondary) cache's ECC (Error Checking and Correction) function, if available.

Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache's ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn't such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor's L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS but it will have no effect.

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How to disable the ECC of L1/L2 Caches of PowerPC P2020 processor?

as stated in the title, how can I disable the ECC (Error Correction Code, or, EDAC, Error Detection and Correction Code) function of the L1 and L2 Caches of a PowerPC P2020 processor? What I already did is:

(1) I read "EREF_RM.pdf", and it states:

For processors which implement ECC for the L1 data cache, ECC is always enabled regardless of the setting of CECE.

So, I figure that the L1 data cache's ECC cannot be disabled; but, can L1 instruction Cache's ECC be disabled?

(2) That same pdf offers the definition of "L2CDEHA" register bits, which says:

L2 cache data error handling available. 00 None 01 Parity detection 10 Single bit ECC correction, 2 bit ECC detection 11 Reserved

So, can I disable L2 cache's ECC with these bits?

asked Sep 15, 2021 at 10:00

user avatar
katyuszakatyusza

32511 silver badge1111 bronze badges

POST Code

Description

CFh

Test CMOS R/W functionality.

C0h

Early chipset initialization:

  • Disable shadow RAM.
  • Disable L2 cache (socket 7 or below).
  • Program basic chipset registers.

C1h

Detect memory:

Auto-detection of DRAM size, type, and ECC.

Auto-detection of L2 cache (socket 7 or below).

C3h

Expand compressed BIOS code to DRAM.

C5h

Call chipset hook to copy BIOS back to E000 and F000 shadow RAM.

01h

Expand the Xgroup codes located in the physical address 1000:0.

02h

Reserved.

03h

Initial Superio_Early_Init switch.

04h

Reserved.

05h

1. Blank out screen.

2. Clear CMOS error flag.

06h

Reserved.

07h

1. Clear 8042 interface.

2. Initialize 8042 self-test.

08h

1. Test special keyboard controller for Winbond 977 series Super I/O chips.

2. Enable keyboard interface.

09h

Reserved.

0Ah

1. Disable PS/2 mouse interface (optional).

2. Auto-detect ports for keyboard and mouse, followed by a port and interface swap (optional).

3. Reset keyboard for Winbond 977 series Super I/O chips.

0Bh

Reserved.

0Ch

Reserved.

0Dh

Reserved.

0Eh

Test F000h segment shadow to see whether it is read/write-able. If test fails, keep beeping the speaker.

POST Code

Description

0Fh

Reserved.

10h

Auto-detect flash type to load appropriate flash R/W codes into the runtime area in F000 for ESCD and DMI support.

11h

Reserved.

12h

Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override.

13h

Reserved.

14h

Program chipset disabling l2 cache ecc error checking values into chipset. Chipset default values are MODBINable by OEM customers.

15h

Reserved.

16h

Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26h.

17h

Reserved.

18h

Detect CPU information, including brand, SMI type (Cyrix or Intel), and CPU level (586 or 686).

19h

Reserved.

1Ah

Reserved.

1Bh

Initial interrupts vector table. If no special is specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR and S/W interrupts to SPURIOUS_soft_HDLR.

1Ch

Reserved.

1Dh

Initial EARLY_PM_INIT switch.

1Eh

ibm thinkpad t42 fan error.

1Fh

Load keyboard matrix (notebook platform).

20h

Reserved.

21h

HPM initialization (notebook platform).

22h

Reserved.

23h

1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute.

2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.

24h

Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, consider the ESCD's legacy information.

POST Code

Description

25h

Early PCI initialization:

  • Enumerate PCI bus number.
  • Assign memory and I/O resource.
  • Search for a valid VGA device and VGA BIOS, and put it into C000:0.

26h

1. If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization. Disable respective clock resource to empty PCI and DIMM slots.

2. Init onboard PWM.

3. Init onboard H/W monitor sl-c3000 hdd2 error.

27h

Initialize INT 09 buffer.

28h

Reserved.

29h

1. Program CPU internal MTRR (P6 and PII) for 0-640K memory address.

2. Initialize the APIC for Pentium class CPU.

3. Program early chipset according to CMOS setup. Example: onboard IDE controller.

4. Measure CPU speed.

2Ah

Reserved.

2Bh

Invoke video BIOS.

2Ch

Reserved.

2Dh

1. Initialize double-byte language font (optional).

2. Put error 5200 canon mp 270 on screen display, including award title, CPU type, disabling l2 cache ecc error checking, CPU speed, full-screen logo.

2Eh

Reserved.

2Fh

Reserved, disabling l2 cache ecc error checking. disabling l2 cache ecc error checking rowspan="1" colspan="1">

30h

Reserved.

31h

Reserved.

32h

Reserved.

33h

Reset keyboard if Early_Reset_KB is defined- for example, Winbond 977 series Super I/O chips. See also POST 63h.

34h

Reserved.

35h

Test DMA Channel 0.

36h

Reserved.

37h

Test DMA Channel 1.

POST Code

Description

38h

Reserved.

39h

Test DMA page registers.

3Ah

Reserved.

3Bh

Reserved.

3Ch

Test 8254.

3Dh

Reserved.

3Eh

Test 8259 interrupt mask bits for channel 1.

3Fh

Reserved.

40h

Test 8259 interrupt mask bits for channel 2.

41h

Reserved, disabling l2 cache ecc error checking.

42h

Reserved.

43h

Test 8259 functionality.

44h

Reserved, disabling l2 cache ecc error checking.

45h

Reserved.

46h

Reserved, disabling l2 cache ecc error checking.

47h

Initialize EISA slot.

48h

Reserved.

49h

1. Calculate total memory by testing the last double word of each 64K page.

2. Program the write allocation for AMD K5 CPU.

4Ah

Reserved.

4Bh

Reserved.

4Ch

Reserved.

4Dh

Reserved.

4Eh

1. Program MTRR of M1 CPU.

2. Initialize L2 cache for P6 class CPU, and program CPU with proper cacheable range.

3. Initialize the APIC for P6 class CPU.

4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical.

4Fh

Reserved.

POST Code

Description

50h

Initialize USB keyboard and mouse.

51h

Reserved.

52h

Test all memory (clear all extended memory to 0).

53h

Clear password according to H/W jumper (optional).

54h

Reserved.

55h

Display number of processors (multiprocessor platform).

56h

Reserved.

57h

1. Display PnP logo.

2. Early ISA PnP initialization -Assign CSN to every ISA PnP device.

58h

Reserved.

59h

Initialize the combined Trend Anti-Virus code.

5Ah

Reserved.

5Bh

(Optional feature) Show message for entering AWDFLASH.EXE from FDD.

5Ch

Reserved.

5Dh

1. Initialize Init_Onboard_Super_IO.

2. Initialize Init_Onboard_AUDIO.

5Eh

Reserved.

5Fh

Reserved.

60h

Okay to enter setup utility; that is, it is not until this POST stage can users enter the CMOS setup utility.

61h

Reserved.

62h

Reserved.

63h

Reset keyboard if Early_Reset_KB is not defined.

64h

Reserved.

65h

Initialize PS/2 mouse.

66h

Reserved.

67h

Prepare memory size information for function call: INT 15h ax=E820h.

68h

Reserved.

69h

Turn on L2 cache.

6Ah

Reserved.

POST Code

Description

6Bh

Program chipset registers according to items described in Setup and
auto-configuration table.

6Ch

Reserved

6Dh

1. Assign resources to all ISA PnP devices.

2. Auto-assign ports to onboard COM ports if the corresponding item in Setup is set to AUTO.

6Eh

Reserved.

6Fh

1. Initialize diskette controller.

2. Set up diskette-related fields in 40:hardware.

70h

Reserved.

71h

Reserved.

72h

Reserved.

73h

Reserved, disabling l2 cache ecc error checking.

74h

Reserved, disabling l2 cache ecc error checking.

75h

Detect and install all IDE devices: HDD, LS120, ZIP, CD-ROM, and so on.

76h

(Optional feature) Enter AWDFLASH.EXE if:

  • AWDFLASH.EXE is in diskette drive.
  • You press ALT+F2.

77h

Detect serial ports and parallel ports.

78h

Reserved.

79h

Reserved.

7Ah

Detect and install coprocessor.

7Bh

Reserved.

7Ch

Initialize HDD write-protect.

7Dh

Reserved.

7Eh

Reserved.

7Fh

Switch back to text mode if full screen logo is supported.

If errors occur, report errors and wait for keys

If no errors occur or F1 key is pressed to continue: Clear EPA or customization logo.

80h

Reserved.

81h

Reserved.

POST Code

Description

E8POST.ASM starts

82h

1. Call chipset power management hook.

2. Recover the text font used by EPA logo (not for full-screen logo). disabling l2 cache ecc error checking. If password is set, ask for password.

83h

Save all data in stack back to CMOS.

84h

Initialize ISA PnP boot devices.

85h

1. Do the USB final initialization.

2. Switch screen back to text mode, disabling l2 cache ecc error checking.

86h

Reserved.

87h

NET PC: Build SYSID structure.

88h

Reserved.

89h

1. Assign IRQs to PCI devices.

2. Set up ACPI table at top of the memory.

8Ah

Reserved.

8Bh

1. Invoke all ISA adapter ROMs.

2. Invoke all PCI ROMs (except VGA).

8Ch

Reserved.

8Dh

1. Enable/disable Parity Check according to CMOS setup.

2. Initialize APM.

8Eh

Reserved.

8Fh

Clear noise of IRQs.

90h

Reserved.

91h

Reserved.

92h

Reserved.

93h

Read HDD boot-sector information for Trend Anti-Virus code.

94h

1. Enable L2 cache.

2. Program daylight saving.

3. Program boot-up speed.

4. Initialize final Chipset.

5. Initialized final power management.

6. Clear screen and display summary table.

7. Program K6 write allocation.

8, disabling l2 cache ecc error checking. Program P6 class write combining.

POST Code

Description

95h

Update keyboard LED and typematic rate.

96h

1. Build MP table.

2. Build and update ESCD.

3. Disabling l2 cache ecc error checking CMOS century to 20h or 19h.

4. Load CMOS time into DOS timer tick.

5. Build MSIRQ routing table.

FFh

Boot attempt (INT 19h).

He is referring to the L2 cache - not main memory. Personally I'd leave it enabled.



<< however, if you just have a normal computer, you may want to disable ecc as it causes a performance drop. (for future reference, buy normal ram, not ecc, if you dont need it for a server, because its cheaper) >>

The performance drop is negligible (on the order of 1%). The price difference nowadays is pretty negligible too:

Crucial.Com 168-pin DIMM:
256MB CAS 2, unbuffered, ECC: $43.19
256MB CAS 2, unbuffered, non-parity: $41.39

So, essentially a ~4% increase gets you ECC.

ECC is useful for anyone who values the data and uptime of their computer, not just servers. If the computer is used for any important task, then I recommend ECC. With prices being what they are, and the performance drop being essentially insignificant (it's within the margin of error on most benchmarks), I don't think there's a strong case for not getting ECC if your motherboard supports it. If it saves you from one just one problem with your computer over the lifetime you own it, then it's more than paid for itself.


Thanks for bringing that back from the dead, Sugadaddy. That was definitely the best discussion of ECC that I have seen on this BBS

Patrick Mahoney
IPF Microprocessor Design Engineer
Intel Corp.

 

58684 - Zynq-7000 Example Design - DDRC ECC Error Test (Inserting Correctable/Uncorrectable Error)

When DDRC detects a correctable ECC error, it automatically corrects the error and sends back the corrected data to the bus master.

When DDRC detects an uncorrectable ECC error, it returns a SLVERR response to the bus master with the uncorrectable data. If L2 cache is disabled, CPU receives the SLVERR response directly and it causes Data Abort. If L2 cache is enabled, L2 cache reports the SLVERR by issuing an interrupt to CPU.

For both correctable and uncorrectable cases, information regarding the error (such as column, row and bank error address, error byte lane, etc.) is logged in the controller register space.

This sample test program tests the ECC error detection by inserting error bits into DDR memory.

It also provides:

  • Interrupt handler for SLVERR interrupt from L2 cache
  • Data Abort handler
  • How to check the error information in DDRC registers

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.

Limited support is provided by Xilinx on these Example Designs.

Design TypePS Only
disabling l2 cache ecc error checking colspan="1">SW TypeStandalone
CPUsSingle CPU @ 667MHz
PS FeaturesDDRC, L2 Cache, GIC, OCM, UART
PL CoresNone
Boards/ToolsZC706
Xilinx Tools VersionVivado 2013.3
Other detailsdisabling l2 cache ecc error checking rowspan="1" colspan="4">Files Provided
ZC706.zip

Archived Vivado project

ddrc_ecc_test.c

Source code
1_CORRECTABLE_CACHE_ON.logSerial output for correctable error test with L2 Cache enable
2_CORRECTABLE_CACHE_OFF.logSerial output for correctable error test with L2 Cache disable
3_UNCORRECTABLE_CACHE_ON.logSerial output for uncorrectable error test with L2 Cache enable
4_UNCORRECTABLE_CACHE_OFF.logSerial output for uncorrectable error test with L2 Cache disable

 

CPU L2 Cache ECC Checking

Common Options : Enabled, Disabled

Quick Review

This BIOS feature enables or disables the L2 (Level 2 or Secondary) cache's ECC (Error Checking and Correction) function, if available.

Enabling this feature is recommended because it will detect and correct overriding virtual method delphi error errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache's ECC function should catch and correct almost all single-bit errors in the memory subsystem.

It will also detect double-bit errors although it cannot correct them. But this isn't such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.

So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.

Please note that the presence of this feature in the BIOS does not necessarily mean that your processor's L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS but it will have no effect.

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And shame!: Disabling l2 cache ecc error checking

Checksum error on database page
Error namber 1146
Disabling l2 cache ecc error checking
Curl_errno7, curl_errorcouldnt connect to host
Bus error core dumped unix

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