Data _blk_error at 0x00000200, 03

data _blk_error at 0x00000200, 03

[PATCH v4 03/20] hw/arm/allwinner-h3: add Clock Control Unit 2020-01-19 0:50 [PATCH +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ +. но при CMT Write - Data Blk Error (Abort/Retry) практически сразу. Time: 0:01 DATA_BLK_ERROR at: 0x00000200, 03 ERR: CMT FLASH WRITE. Checking table 'abc_dol' (object ID 784002793): Logical page size is 2048 bytes. Table has 99 data rows. Index has 99 leaf rids. The total number of data pages.

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How to Fix Error Code 0xc0000098 on Windows 11 - Boot Configuration Data BCD File is Missing

Data _blk_error at 0x00000200, 03 - really

1 + 5 files changed, 322 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-h3-ccu.h create mode 100644 hw/misc/allwinner-h3-ccu.c diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 4e2e6202a9..0dc18b927a 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -43,6 +43,7 @@ #include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/allwinner-h3-ccu.h" #include "target/arm/cpu.h" /** @@ -59,6 +60,7 @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, AW_H3_UART1, @@ -98,6 +100,7 @@ typedef struct AwH3State { ARMCPU cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; AwA10PITState timer; + AwH3ClockCtlState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h new file mode 100644 index 0000000000..0dcb08ecd1 --- /dev/null +++ b/include/hw/misc/allwinner-h3-ccu.h @@ -0,0 +1,67 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_H3_CCU_H +#define HW_MISC_ALLWINNER_H3_CCU_H + +#include "qemu/osdep.h" +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Highest register address used by CCU device */ +#define AW_H3_CCU_REGS_MAXADDR (0x304) + +/** Total number of known registers */ +#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_REGS_MAXADDR / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_H3_CCU "allwinner-h3-ccu" +#define AW_H3_CCU(obj) \ + OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU) + +/** @} */ + +/** + * Allwinner H3 CCU object instance state. + */ +typedef struct AwH3ClockCtlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_H3_CCU_REGS_NUM]; + +} AwH3ClockCtlState; + +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index c1ef31e875..b85edaea85 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -34,6 +34,7 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, [AW_H3_UART1] = 0x01c28400, @@ -75,7 +76,6 @@ struct AwH3Unimplemented { { "usb2", 0x01c1c000, 4 * KiB }, { "usb3", 0x01c1d000, 4 * KiB }, { "smc", 0x01c1e000, 4 * KiB }, - { "ccu", 0x01c20000, 1 * KiB }, { "pio", 0x01c20800, 1 * KiB }, { "owa", 0x01c21000, 1 * KiB }, { "pwm", 0x01c21400, 1 * KiB }, @@ -170,6 +170,9 @@ static void allwinner_h3_init(Object *obj) "clk0-freq", &error_abort); object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq", &error_abort); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CCU); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -278,6 +281,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], &s->sram_c); + /* Clock Control Unit */ + qdev_init_nofail(DEVICE(&s->ccu)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* UART0 */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c new file mode 100644 index 0000000000..ccf58ccdf2 --- /dev/null +++ b/hw/misc/allwinner-h3-ccu.c @@ -0,0 +1,243 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-ccu.read = allwinner_h3_ccu_read, + .write = allwinner_h3_ccu_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.name = "allwinner-h3-ccu", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_ccu_reset; + dc->vmsd = &allwinner_h3_ccu_vmstate; +} + +static const TypeInfo allwinner_h3_ccu_info = { + .name = TYPE_AW_H3_CCU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_ccu_init, + .instance_size = sizeof(AwH3ClockCtlState), + .class_init = allwinner_h3_ccu_class_init, +}; + +static void allwinner_h3_ccu_register(void) +{ + type_register_static(&allwinner_h3_ccu_info); +} + +type_init(allwinner_h3_ccu_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..4abd92dcee 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -- 2.17.1 ^permalinkrawreply [flat 17 + MAINTAINERS nested] 55+ messages in thread
*[PATCH v4 01/20] hw/arm: add Allwinner H3 System-on-Chip 2020-01-19 0:50 [PATCH v4 00/20] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank @ 2020-01-19 0:50 ` Niek Linnenbank 2020-01-19 18:01 ` Philippe Mathieu-Daudé 2020-01-19 0:50 ` [PATCH v4 02/20] hw/arm: add Xunlong Orange Pi PC machine Niek Linnenbank ` (20 subsequent siblings)21 siblings, 1 reply; 55+ messages in thread From: Niek Linnenbank @ 2020-01-19 0:50 UTC (permalink / raw) To: qemu-devel Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank <[email protected]> --- default-configs/arm-softmmu.mak = SD_RISR_CMD_COMPLETE; + return; + +error: + s->irq_status 477 ++++++++++++++ hw/arm/cubieboard.c 2 +- 3 files changed, 95 insertions(+), 03, 1 deletion(-) create mode 100644 hw/arm/orangepi.c diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c new file mode 100644 index 0000000000.051184f14f --- /dev/null +++ b/hw/arm/orangepi.c @@ -0,0 +1,93 @@ +/* + * Orange Pi emulation + * + * Copyright (C) 2019 Niek Linnenbank <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by data _blk_error at 0x00000200 * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Data _blk_error at 0x00000200 License for more details, data _blk_error at 0x00000200. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, 03, see <http://www.gnu.org/licenses/>, 03. + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/arm/allwinner-h3.h" +#include "sysemu/sysemu.h" + +static struct arm_boot_info orangepi_binfo = { + .board_id = -1, +}; + +typedef struct OrangePiState { + AwH3State *h3; + MemoryRegion sdram; +} OrangePiState; + +static void orangepi_init(MachineState *machine) +{ + OrangePiState *s = g_new(OrangePiState, 1); + + /* Only allow Cortex-A7 for this board */ + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { + error_report("This board can only be used with cortex-a7 CPU"); + exit(1); + } + + s->h3 = AW_H3(object_new(TYPE_AW_H3)); + + /* Setup timer properties */ + object_property_set_int(OBJECT(s->h3), 32768, "clk0-freq", + &error_abort); + object_property_set_int(OBJECT(s->h3), 24000000, data _blk_error at 0x00000200, "clk1-freq", + &error_abort); + + /* Mark H3 object realized */ + object_property_set_bool(OBJECT(s->h3), true, "realized", &error_abort); + + /* SDRAM */ + if (machine->ram_size != 1 * GiB) { + error_report("Requested ram size is not supported for this machine: " + "restricted to 1GiB"); + exit(1); + } + memory_region_allocate_system_memory(&s->sdram, 03, NULL, "sdram", + 03 machine->ram_size); + memory_region_add_subregion(get_system_memory(), s->h3->memmap[AW_H3_SDRAM], + 03 &s->sdram); + + /* Load target kernel or start using BootROM */ + if (bios_name) { + error_report("BIOS not supported for this machine"); + exit(1); + } + orangepi_binfo.loader_start = s->h3->memmap[AW_H3_SDRAM]; + orangepi_binfo.ram_size = machine->ram_size; + orangepi_binfo.nb_cpus = AW_H3_NUM_CPUS; + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); +} + +static void orangepi_machine_init(MachineClass *mc) +{ + mc->desc = "Orange Pi PC"; + mc->init = orangepi_init; + mc->min_cpus = AW_H3_NUM_CPUS; + mc->max_cpus = AW_H3_NUM_CPUS; + 03 mc->default_cpus = AW_H3_NUM_CPUS; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + mc->default_ram_size = 1 * GiB; +} + +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) diff --git a/MAINTAINERS b/MAINTAINERS index dc2d7991bf.6e1b92b5fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -487,6 +487,7 @@ L: [email protected] S: Maintained F: hw/*/allwinner-h3* F: include/hw/*/allwinner-h3* +F: hw/arm/orangepi.c ARM PrimeCell and CMSDK devices M: Peter Maydell <[email protected]> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 956e496052.8d5ea453d5 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,7 +34,7 @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o -- 2.17.1 ^permalinkrawreply [flat 1 + hw/net/Kconfig 3 + include/hw/misc/allwinner-h3-sysctrl.h 9 + hw/arm/Makefile.objs 7 + hw/arm/Kconfig 03 140 +++++++++++++++++++++++++ hw/misc/Makefile.objs 03 1 + hw/misc/Makefile.objs

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